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Design Languages >> Verilog-AMS >> Verilog-A: Instantiating Primitive Analog
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Message started by Hisham on Jul 26^th, 2004, 3:35am

Title: Verilog-A: Instantiating Primitive Analog
Post by Hisham on Jul 26^th, 2004, 3:35am

I am experimenting the verilog-A. Here is my simple code for implementing
nmos by instantiating primitive nmos (modn) in my code:

`include "constants.h"
`include "discipline.h"
module nmos4(B, D, G, S);
inout B,D,G,S;
electrical B,D,G,S,Dr;
real Idsn;
mywire wr (D,Dr);
modn nmos1 (Dr,G,S,B);
analog begin
Idsn=I(D,Dr);
end
endmodule

This is fine. But what I need to to be able to trace the tranconductace (gm) of the modn.

Please help

Hisham

Title: Re: Verilog-A: Instantiating Primitive Analog
Post by Geoffrey_Coram on Sep 1^st, 2004, 5:57am

Hisham -
I assume "nmos1" is resolved to a .model card referencing a primitive (Spice) mosfet?

You've essentially made a subcircuit here, and it's probably implementation-dependent as to whether the simulator allows you to "see" inside a Verilog-A subcircuit to print operating-point information.

There are some compact modeling extensions for Verilog-A that have been submitted to the Accellera board; they include a method of declaring operating-point variables for a module.

-Geoffrey