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Design >> Mixed-Signal Design >> voltage reference buffer for pipelined ADC
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Message started by ywguo on Aug 22^nd, 2004, 6:14pm

Title: voltage reference buffer for pipelined ADC
Post by ywguo on Aug 22^nd, 2004, 6:14pm

Hi,

I have got a little problem in designing the reference voltage buffer for 10 bits - 40M, pipeline A/D converter, and hope you could help me for better understanding.

As you know, the voltage references in an SC data converter need to charge and discharge a capacitor, so to achieve very high speed and resolution from a pipeline A/D converter, the MDAC reference voltages (their values are 2.1v, 1.1v for my application) must be buffered in order to attain the required accuracy and settling time. My reference voltages (their values are 2.1v, 1.1v for my application) are generated by an on-chip bandgap reference.

The problem came up when I was making the specification for my buffer of the MDAC reference voltages. I plan to realize my buffer by using a three-stage cascade operational amplifier in feedback in order to provide low output impedance. And the problem is I am just not sure how much the unity-gain bandwidth my buffer needs. Especially when I want to use a buffer combined with an external stabilization capacitor.

The reasons I am not sure about the unity-gain bandwidth are:

1, I think we just need to buffer a dc voltage (like 2.1v), so I don’t think the buffer should be fast.

2, When I use an external stabilization capacitor, apparently the speed of the buffer is slowed down, but the variations at the output of the buffer seemed to be decreased.

So I am really puzzled, I am really not sure how much the unity-gain bandwidth my buffer needs when I use a huge external stabilization capacitor.

I hope you could help me to get a little more insight.

Best regards,
Yawei Guo

Title: Re: voltage reference buffer for pipelined ADC
Post by Paul on Aug 25^th, 2004, 12:51pm

Hello Yawei,

as you have a capacitive load only (I believe), output impedance is important, but not the only spec to take care of. The major specifications for charging switched capacitors are slew-rate and settling time. The latter is directly related to the unity gain frequency (or gain-bandwidth product) of your buffer. You should thus design a buffer with sufficient gain-bandwidth, which is easier to do with 1 or 2 stages. You can achieve low output impedance with these kind of topologies too, you don't need three stages.

Have a look at Laker and Sansen, "Design of Analog Integrated Circuits and Systems", which I would suggest to be added to the bookshelf. For some technical reason my e-mail with reference books is not getting to the administrator... It has good explanations about amplifier design and gain-bandwidth trade-offs.

Paul

Title: Re: voltage reference buffer for pipelined ADC
Post by Forum Administrator on Aug 25^th, 2004, 6:33pm

I have added the Laker-Sansen book to the Bookshelf, though it appears to be out-of-print. Hopefully they are working on a new edition.

Title: Re: voltage reference buffer for pipelined ADC
Post by Art Schaldenbrand on Sep 22^nd, 2004, 8:10pm

Yawei,

The design is overconstrained. That is when considering the overall reference design there are two poles: the buffer pole and the pole due to the bypass capacitor at the reference node. Instead of designing a super fast buffer that can drive an infinte load, it may be easier to use another approach. For example, use a simple operational transconductance amplifier[OTA]. The OTA controls the dc characteristics of the system, the external capacitor provides bypassing and controls the high frequency characterisitics, and there is only one pole set by OTA gm/ Bypass Capacitor C.
To get accurate results, it is critical that you correctly model the capacitor, the package, the board, ..., the capacitor may not be a "capacitor" when parastics are considered.

Best Regards,

Art

Title: Re: voltage reference buffer for pipelined ADC
Post by codec on Oct 24^th, 2004, 5:45am

I used to think buffer AMP is adequate for such application referrng to simulation result. (2stage Buffer AMP Fu~10MHz).
However, today when goingthrough datasheets of comercial products from TI, LTC and NS, I found that they would use off-chip bypass cap. of 0.1u~1.0u. What do you think of the AMP structure inside their chip? It is hard to design a buffer AMP with such large loading, isn't? I wonder whether or not they are using OTA. But, to generate VP and VN by resistive voltage divisiotn, it is difficult to guaratee high gain in fully differential OTA. If VP and VN is generated first and then buffered by OTA, it needs more layout area.
I hope to simulate my design with OTA buffer if I can squeeze time.
What is your oppion?

Title: Re: voltage reference buffer for pipelined ADC
Post by microant2000 on Nov 10^th, 2004, 5:30am

hello, yawei && codec
the question about voltage reference used in ADC,i think Art Schaldenbrand' ideal is right.
by the way , i have seen the photograph of a chip of ADC , actually the bypass capacitor is used by the output voltage of bandgap,not the reference voltage such as 2.1v, 1.1v in your design. so i think telescopic amplifer is a good choice . how do you think
Best Regards :D
microant

Title: Re: voltage reference buffer for pipelined ADC
Post by vivkr on Dec 17^th, 2005, 1:47am

Hi,

Is there any special advantage of using an on-chip reference buffer? I mean it is needed if one is making a complete product, but if it is just a question of testing the ADC core performance, then it is often easier if the reference voltage can be controlled externally.

I would like to use an off-chip reference converted to fully-differential form and decoupled with large capacitors. Are there any issues I need to worry about other thsn reference modulation and choosing a large enough cap?

Thanks
Vivek

Title: Re: voltage reference buffer for pipelined ADC
Post by rf-design on Dec 18^th, 2005, 5:59am

Beside the question how to spec the buffer the settling performance of the buffer after charpeup of the switched caps will impact the settling behaviour of the first radix stage. So it is not sufficient to test the performance of the remaining stages alone.

Title: Re: voltage reference buffer for pipelined ADC
Post by mists on Dec 18^th, 2005, 10:01pm

then if I use internal buffer for voltage reference without large outside bypass capacitor, then how to spec the settling performance of the buffer that will not affect gain stage amplifier's setting time?

Title: Re: voltage reference buffer for pipelined ADC
Post by rf-design on Dec 20^th, 2005, 4:08am

The settling should be completed up to the resolution depending error within some time. The settling process is then the settling of the buffer and the opamp. Because the buffer has to settle first the complete process takes longer.

Title: Re: voltage reference buffer for pipelined ADC
Post by mists on Dec 21^st, 2005, 12:48am

then how to spec the buffer's setting time? for example, if gain amplifier need to settle it in 8t, how long should the buffer settle? 6t? 7t?

Title: Re: voltage reference buffer for pipelined ADC
Post by huber on Jan 9^th, 2006, 3:44pm

If using a large offchip bypass capacitor, be sure to model series inductance of the bondwire.