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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Fractional Divider in Reference Path of PLL https://designers-guide.org/forum/YaBB.pl?num=1094802750 Message started by Daniel Nobonzo on Sep 10th, 2004, 12:52am |
Title: Fractional Divider in Reference Path of PLL Post by Daniel Nobonzo on Sep 10th, 2004, 12:52am Hi, I wonder if there is any drawback in placing a fractional divider (noise, spurs, ..) in the reference path, i.e. after the crystal, instead of after the VCO. Thanks for your comments. Dan |
Title: Re: Fractional Divider in Reference Path of PLL Post by emad on Sep 10th, 2004, 8:01am It is actually both! A fractional divider based on DS modulation is pretty noisy. That is because the quantization noise shows as shaped noise with 20*(n-1) dB/dec, where n is the modulator order. This noise at the reference will be further magnified by 20*log(N), where N is the feedback divider ratio. Same happens for spurs. For the reference section you want a quiet configuration. You simply can't afford to mess up there. |
Title: Re: Fractional Divider in Reference Path of PLL Post by strabush on Jan 10th, 2005, 5:58am Matter of fact, A DDS as the reference is exactly that. |
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