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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Error encountered during NC elaboration for config https://designers-guide.org/forum/YaBB.pl?num=1097851376 Message started by Vivek Chandrasekhar on Oct 15th, 2004, 7:42am |
Title: Error encountered during NC elaboration for config Post by Vivek Chandrasekhar on Oct 15th, 2004, 7:42am Hello, I have created a toplevel configuration in which i have an ideal ADC generated from code and 4 bit DAC using transistor level schematic. I realize that the four bits coming out from the ideal ADC are logic signals. The inputs to the DAC are electrical signals(Cadence transistor level schematic) and I dont know how to convert the logic signals back to electrical signals. When i run my simulation , i get this error: "No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical". I would be grateful to anyone who could help me solve my problem. Thanks Vivek |
Title: Re: Error encountered during NC elaboration for co Post by Andrew Beckett on Oct 18th, 2004, 5:36am Read the AMS Designer tutorial in the cdsdoc documentation. It explains about the need for connect modules - you've probably not compiled an appropriate connect module and connect rules, or not told it which connect rules to use. Rather than me repeating the docs, look at <instdir>/doc/amsenvug/amsenvug.pdf (I think it is chapter 2?) Andrew. |
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