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Measurements >> Phase Noise and Jitter Measurements >> phase noise and Jitter measurements in Cadence
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Message started by ppm on Dec 1^st, 2004, 1:48pm

Title: phase noise and Jitter measurements in Cadence
Post by ppm on Dec 1^st, 2004, 1:48pm

Hi everyone... I am glad to have find this website with many experts. i hope you will be able to help me with my current problems with measuring phase noise and jitter. I have read Ken's paper on phase noise and jitter but I still have some questions:

1. First of all, is spectre the same as spectreRF? Please explain the difference. I've been using spectre and have no experience with spectreRF.
2. I was finally able to make my frequency synthesizer locked at 30us. Is this lock time reasonable?
3. My input freq=1.25MHz, out freq=2.4GHz, division ratio=1920. Would it be able to use cadence spectre/spectreRF to get the phase noise? I read from Ken's paper that I might have convergence issue with division ratio > 10. If this can be done, could you please tell me the steps to setup spectre/RF to get the phase noise. I am not sure how to configure PSS and the PNOISE as you mentioned in your paper. Pl
4. Can you please tell me the setup to measure Jitter in Cadence also?

I don't have that much time to test everything out as I need to get these results ASAP to prepare for a Thesis presentation on Monday, Dec 6. I would appreciate it very much if you can advise me the best way to get the phase noise and jitter results while still able to meet my deadline.
Thanks and Best Regards,
Pei-Ping Mo
ps... my university doesn't support verilog... so I can't test out the modules that Ken wrote. Thanks again. Hope to hear from you soon.

Title: Re: phase noise and Jitter measurements in Cadence
Post by ppm on Dec 3^rd, 2004, 12:09pm

no answers ??? :(

Well, here is another dumb question from an inexperienced designer.

should I set tstat =30us if my PLL locks around that time?

Thanks.

ppm

Title: Re: phase noise and Jitter measurements in Cadence
Post by Ken Kundert on Dec 3^rd, 2004, 2:03pm

1. SpectreRF is an option to Spectre. When you get SpectreRF you get additional analyses such as PSS and PNoise.

2. 30us corresponds to 40 cycles, which seems reasonable. But of course the required lock time would depend on the intended application.

3. SpectreRF would not necessarily have convergence problems on a synthesizer with a divide ratio of 1920, but it would likely run out of memory and would just take too long.

The process for simulating a PLL is described in the paper in much more detail that is practical to give here (that is why I wrote the paper). If you don't understand the process, try to ask specific questions. Open ended questions such as these are impractical to answer in this medium.

4. Jitter measurement is also covered in the papers. Please ask specific questions.

5. If your lock time is 30us, then tstab should be around 30us, perhaps a little longer.

-Ken

Title: Re: phase noise and Jitter measurements in Cadence
Post by ppm on Dec 3^rd, 2004, 10:28pm

Ken, thank you very much for your time and explanations. It gives me a peace of mind to know from an expert that the locking time is within a reasonable range.
I am trying to run the PSS/PNOISE in Spectre. It is taking a long time. For my PLL to lock, it took two days to run. I guess this will probably take as long. I will try to ask more specific questions next time after I review your papers more carefully and try out some of methods that you suggested. I am also researching to setup the environments for running the verilog. I think I need a hdl.var file. Not quite sure what to do with that yet. Any suggestions?

Anyway, it is late at night. I think I am just rambling on and on. But I am really happy that you take the time answer my dumb questions ;) Thanks. Have a good weekend.

ppm

Title: Re: phase noise and Jitter measurements in Cadence
Post by Ken Kundert on Dec 4^th, 2004, 12:04am

The modules in the paper are all Verilog-A, which Spectre can handle directly. No need for Verilog itself.

-Ken

Title: Re: phase noise and Jitter measurements in Cadence
Post by mvaibhav on Jan 24^th, 2005, 3:03am

Hi,
I am designing a VCO in 0.13u STM process and want to do phase noise measurements in cadence. I could not fully understand the setup for phase noise measurement. It seems to me that it is given in detail in Ken's paper. Could you please tell me how I can get this paper.

Thanks.
Vaibhav

Title: Re: phase noise and Jitter measurements in Cadence
Post by Ken Kundert on Jan 24^th, 2005, 4:33pm

Look in http://www.designers-guide.com/Analysis/.

-Ken

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 23^rd, 2005, 11:26pm

Hello Ken and all experts,
Can SpectreRF PSS/PNoise simulate the verilogA code?
I use a simple VCO behavior model, which was modified from the cadence ahdlLib (vco cell).

However, this VCO couldn't converge at the given resonant frequency, so I can't use PNoise for phase noise simulation.

Any suggestion about this?
Sincerely yours,

Daniel Lai

Title: Re: phase noise and Jitter measurements in Cadence
Post by Ken Kundert on Jun 24^th, 2005, 12:48am

SpectreRF has some restrictions that prevent it from simulating certain Verilog-A models. Take a look at http://www.designers-guide.org/Analysis/hidden-state.pdf.

-Ken

Title: Re: phase noise and Jitter measurements in Cadence
Post by Andrew Beckett on Jun 24^th, 2005, 2:09pm

If I remember rightly, the problem with the vco model was not that it had hidden states, but that the phase was not periodic. It used idt() rather than idtmod() to integrate the voltage converted to frequency to obtain the phase; idtmod allows the phase to be cyclic.

Recent versions of ahdlLib have a spectreRF-friendly vco model, I think (I'm not at work, so can't check right now).

Regards,

Andrew.

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 26^th, 2005, 10:45pm

dear Ken and Andrew,
Thanks very much for your early reply.

I used the ahdlLib vco verilogA model, and set the input terminal to ground.
The vco outputs pure sinusodal signal without noise, and it works perfect in transient analysis.
However, this vco model wouldn't converge when PSS analysis.
It seems the hidden states in SpectreRF are complicated, so we can't define and reformulate what kinds of states cause problems easily.
I still don't understand why the vco model in ahdlLib cannot converge in this case.

Besides, as Andrew mentioned in the reply, the vco model in ahdlLib uses idt() instead of idtmod(), and described as below:

phase_nonlin= 2*pi* vco_gain* idt(V(vin),0)

However, if we want to use idtmod(), we should specify a modulus value.
(idtmod() behaves like the idt() and performs no limiting on the output of the integrator.) ref. Verlog A manual.
I modified it to idtmod() and run a PSS simulation, but it still not converge.

I think verilogA can run transient analysis in transient easily, but seems difficult to do PSS analysis to a easy periodical signal.
I don't know if you have better idea or suggest one vco model avoiding the hidden state.

Orz
(You are such famous experts and answer my question so quickly. That's awful honor to me and I am very appreciated to your advice.)

Daniel Lai

Title: Re: phase noise and Jitter measurements in Cadence
Post by Ken Kundert on Jun 27^th, 2005, 7:55am

Daniel,
Did you put in a value for the modulus argument? It appears as if you should use the value of 1.

-Ken

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 27^th, 2005, 7:26pm

Hi Ken, (Orz)

Thanks very much for your advice, again.
I tried to modify the modulus number, but it still not converged. Then I tried to delelte the idt() or idtmod(), to make phase_nonlin constant, but it still not converged, either.

I am sorry that I didn't specify the simulation siuation to you.
Part of the verilogA code of VCO is described below:

module VCO_bhvmdl(vtune, vref, vout, voutb);
input vtune, vref;
output vout, voutb;
electrical vtune, vref, vout, voutb;
parameter real amp = 150m;
parameter real fc = 864K;
parameter real Kvco = 227K;
parameter real Vcomm = 1;
real wc; // center freq in rad/s

real phase_lin; // wc*time component of phase
real phase_nonlin; // the idt(k*f(t)) of phase

integer num_cycles; // number of cycles in linear phase component

real inst_freq; // instanteous frequency
analog begin

@ ( initial_step ) begin
wc = 2 * `PI * fc;
end

//
// linear portion is calculated so that it remains in the +/- 2`PI range
// This is to ensure it's value doesn't get too large and cause rounding
// problems for calculation of the phase.
//
phase_lin = wc * $abstime;
num_cycles = phase_lin / (2*`PI);
phase_lin = phase_lin - num_cycles * 2 * `PI;

phase_nonlin = 2 * `PI * Kvco * idtmod( V(vtune, vref), 0, 1 );
// phase_nonlin = 0;
V(vout) <+ Vcomm + amp * sin (phase_lin + phase_nonlin);
V(voutb) <+ Vcomm + amp * sin (phase_lin + phase_nonlin + `PI);
//
// ensure that modulator output recalculated soon.
//
inst_freq = fc + Kvco * V(vtune, vref);
$bound_step (0.02 / inst_freq);
end
endmodule

The VCO has differential input, and I tied them together to ground. So this vco oscillates only 864KHz without any noise.

In transient simulation, the vco oscillates perfect at 864KHz, and no time delay. However in PSS analysis, no matter what value I set in tstab (1us, 5us, 20us, 100us), it cannot work.

The simulation file is described below:

simulator lang=spectre
global 0
include "/.../artist/ahdlLib/quantity.spectre"

I0 (0 0 out outb) VCO_bhvmdl
ic out=1.01 outb=1
simulatorOptions options reltol=1e-5 vabstol=1e-8 iabstol=1e-13 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
tran tran stop=10u write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
pss ( out outb ) pss fund=864K harms=10
+ errpreset=conservative tstab=10u saveinit=yes method=gear2only
+ tstabmethod=gear2only annotate=status
pnoise ( out outb ) pnoise sweeptype=relative relharmnum=1
+ start=10 stop=100M dec=10 maxsideband=4 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
saveOptions options save=allpub

Thank you very much for your kindly help.
Sincerely yours,
Daniel Lai

Title: Re: phase noise and Jitter measurements in Cadence
Post by Andrew Beckett on Jun 27^th, 2005, 11:10pm

The problem is that the period for the idtmod to reset itself is not the same as the period of the instantaneous frequency in your code.

Here's how the newer vco model does it (this is all that is in the analog block in the new model):

Code:

inst_freq = center_freq + vco_gain * V(vin);
$bound_step (1.0 / (steps_per_period*inst_freq));

phase = idtmod(inst_freq,0,1);
V(vout) <+ amp * sin (2 * `PI * phase);

As you can see, the idtmod is integrating the calculated instantaneous frequency, with a modulus of 1, and so it will reset the phase at the end of each period - consequently the variable phase is co-periodic with the output voltage of the VCO.

Regards,

Andrew.

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 28^th, 2005, 6:14pm

Thank you very much, Andrew and Ken. ( ;D)

The new vco model proposed by Andrew solved the PSS non-convergence problem.

As Andrew mentioned before, idtmod allows the phase to be cyclic. Does that mean only periodic signal (or noise) could be analyzed in PSS analysis?

Best regards,
Daniel Lai

Title: Re: phase noise and Jitter measurements in Cadence
Post by Andrew Beckett on Jun 28^th, 2005, 11:03pm

Well, yes - the "P" in PSS does stand for periodic...

Note, the noise is small-signal, so you don't have to worry about that in the PSS analysis itself - it is only applied during the pnoise/psp analyses.

You can have non-periodic sources for (say) startup of the circuit - PSS will simulate these until they become periodic (or constant) - essentially you're trying to find the steady state of the circuit - so things need to either be constant or repetitive when it tries to analyse that.

Regards,

Andrew.

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 29^th, 2005, 3:48am

Thank you very much, Andrew.

The problem confused me is that we use not only periodic signal but periodic noise for PSS analysis. However, that is an assumption that noise should be periodic at steady state.
Does that mean only cyclostationary noise could be applied on this vco model? Stantionary noise couldn't due to no periodical information. (So we need to use idtmod() instead of idt() in PSS analysis.)

Best regards,
Daniel Lai

Title: Re: phase noise and Jitter measurements in Cadence
Post by Andrew Beckett on Jun 29^th, 2005, 6:13am

The term "periodic noise analysis" is referring to the fact that you are doing a noise analysis about a periodic steady state; it is not referring to the noise itself being periodic.

Mind you, I'm not entirely sure I understood what you said in your last append.

Regards,

Andrew.

Title: Re: phase noise and Jitter measurements in Cadence
Post by chlai on Jun 30^th, 2005, 8:00pm

Hello Andrew,
Thank you very much for answering me so many questions.

Because idtmod() means to integrate the peridic signal and noise in one cycle (of period), which also means to make all input noise become cyclostationary noise.

My problem is: Can we determine all input noise (including flicker noise, white noise) become cyclic in this vco model. If the answer is no, would the vco model generate error phase noise analysis result?
I think this is a cyclostationary noise definition question. Sorry to confuse you.

Thank you very much for your kindly interested.
Sincerely yours,
Daniel Lai