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Design Languages >> Verilog-AMS >> Running V-AMS simulations
https://designers-guide.org/forum/YaBB.pl?num=1102999701

Message started by Vikram Srinivasan on Dec 13^th, 2004, 8:48pm

Title: Running V-AMS simulations
Post by Vikram Srinivasan on Dec 13^th, 2004, 8:48pm

I'm trying to run V-AMS codes on SimVision in Cadence...i give my sine wave input as:

vsource #(.type("sine"),.dc(0),.amp(5),.val1(5),.val0(-5),.freq(5000)) vin(in,gnd);

now i see a sine wave as an input but it has an amplitude of only 1volt...iv tried everything possible..what could be wrong?

also,how can i get layout designs for v-ams codes which function properly?is there an option in simvision or any other tool that i can use to get a ciruit layout for a given code?

lastly,the testbenches for the sample codes on this website seem to be written out for spectre. is this a better tool than simvision?

i'd reallly like to learn from a verilog ams tutorial, if there is one online....resources seem to be very limited save this book and the LRM !!!

thanks again!

vikram

Title: Re: Running V-AMS simulations
Post by Ken Kundert on Dec 13^th, 2004, 11:12pm

Vikram,
I think you want ampl(5) rather than amp(5).

Concerning the test benches on this website, some are for Spectre and some are for AMS Designer (what you call SimVision). Spectre only supports Verilog-A not Verilog-AMS, and the test benches for the Verilog-A models are given for Spectre.

Spectre is limited to simulating transistor level netlists and Verilog-A models, but can all the SPICE and RF analyses (such as AC, Noise, etc.)

AMS Designer is currently limited to running transient analysis, but can simulate Verilog, VHDL, Verilog-AMS and VHDL-AMS descriptions as well as transistor-level netlists.

Concerning online tutorials, I don't know of any.

-Ken

Title: Re: Running V-AMS simulations
Post by Vikram Srinivasan on Dec 14^th, 2004, 12:15pm

Hi Ken

Thanks a LOT ! That was really helpful. I'm going to use the "Designer's guide" to learn Verilog-AMS completely..and it seems like SimVision might be the best tool for me to complie my codes.

Now when you say that this tool can simulate Verilog-AMS programs...can it just complie them or can it produce a blck diagram layout of the same too? I dont know if my question is specific enough,but I'd like to see circuit layouts drawn by SimVision for the circuit codes that I compile.

Title: Re: Running V-AMS simulations
Post by Ken Kundert on Dec 14^th, 2004, 7:49pm

No, it is just a simulator. It does not generate schematics or block diagrams. If you look around though, you can probably find schematic generators that start with structural verilog.

-Ken

Title: Re: Running V-AMS simulations
Post by Andrew Beckett on Dec 14^th, 2004, 10:08pm

Actually the simvision debugging environment has a schematic tracer which allows you to visualize the connections for selected instances and nets in your Verilog code.

You can select nets/instances in the browser (either the design browser or the code browser, say), and then "send to schematic tracer" (I think that's what the menu says).

Note, this is not a _real_ schematic - just a virtual representation of one in order to allow you to figure out signal flow.

In the DFII environment, there is File->Import->Verilog which would allow you to create a real schematic from structural Verilog (any behavioural blocks will be imported as textual views).

From what you said, I think this is what you were after; if you were after physical layout, then that's the job of a place and route tool (such as the Encounter family from Cadence).

Regards,

Andrew.

Title: Re: Running V-AMS simulations
Post by Ken Kundert on Dec 15^th, 2004, 2:08am

Well, I stand corrected.

Thanks Andrew!

-Ken

Title: Re: Schematic Tool
Post by Vikram Srinivasan on Dec 15^th, 2004, 2:44pm

Hi Andrew and Ken

Thanks for letting me know about the schematic tool for AMS-Design Browser. I tried my resistor code to see what kind of simulation I got... The following are the codes:

Resistor:
`include "disciplines.vams"
`include "constants.vams"
`timescale 10ps/1ps;

module res(pos,neg);
parameter real rn=1k from [0:inf] exclude 0;
electrical pos,neg;
analog
begin
V(pos,neg) <+ rn*I(pos,neg);
end
endmodule

TESTBENCH:
`include "disciplines.vams"
`include "constants.vams"
`timescale 10ps/1ps

module resistortest(p,n);
ground n;
electrical p,n;
res #(rn(100)) resistor(p,n);
vsource#(.type("sine"),.ampl(5),.freq(5000),.dc(0))vin(p,n);
endmodule

Now when I complie this, I see a sine wave for the pos terminal and just a straight line output for neg terminal. The Schematic tool shows that 0 signal comes out of the device from the neg terminal.

Am I doing something wrong?

How can I get V-I characteristics instead of getting Voltage characteristics w.r.t Time?

Vikram

Title: Re: Running V-AMS simulations
Post by Ken Kundert on Dec 15^th, 2004, 5:32pm

Vikram,
The negative terminal should have 0 value as it is grounded. By the way, the way you wrote your resistor, you do not need the "exclude 0" on the resistance parameter.

AMS Designer only performs transient (or time domain) analysis.

-Ken