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Design Languages >> Verilog-AMS >> Parameterizable models in V-AMS
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Message started by Vikram Srinivasan on Dec 26^th, 2004, 5:21pm

Title: Parameterizable models in V-AMS
Post by Vikram Srinivasan on Dec 26^th, 2004, 5:21pm

Can somebody tell me how one can make models in V-AMS parameterizable?As in, when you build circuits in Magic and run them with SPICE,you have the ability to change transistor dimensions to suit your requirements of area/power dissipation/speed etc. What would be the best method to achieve this in V-AMS with the AMS Design Simulator. Specifically, can analog models be made parameterizable?

Title: Re: Parameterizable models in V-AMS
Post by wbear on Jan 28^th, 2008, 4:20pm

If you are using Spectre, changing the parameters of a VerilogA model is very simple -- just open up the property window of your device, select "VerilogA" in the CDF Parameter of View, and all the parameters defined in your model should pop up.