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Design >> Analog Design >> Low 1/f noise CMOS amplifier
https://designers-guide.org/forum/YaBB.pl?num=1105326401

Message started by ywguo on Jan 9^th, 2005, 7:06pm

Title: Low 1/f noise CMOS amplifier
Post by ywguo on Jan 9^th, 2005, 7:06pm

Hi,

I need design a CMOS amplifier with low 1/f noise corner. Thermal noise doesn't matter.

Please give me guide or advise some books, papers.

Thanks
Yawei

Title: Re: Low 1/f noise CMOS amplifier
Post by Ken Kundert on Jan 9^th, 2005, 8:06pm

You could try a chopper stabilized ampifier or correlated double sampling.

-Ken

Title: Re: Low 1/f noise CMOS amplifier
Post by 101questions on Jan 9^th, 2005, 11:08pm

Some auto-zeroing techniques suppress 1/f noise as well. In fact diffrences betweel auto-zero, correlated double sampling and chopper stabilizer are somewhat blurry, the concepts are quite similar.
Generally, consider yourself lucky if you manage to improve 1/f noise by a factor of 5 with these techniques.
Other than that use large area devices, avoid pocket implant mos, if you can. Some might recommend to avoid subthreshold devices, while some others might disagree.
There are also black magic techniques, like gated bias, but they are not in the model, so only silicon would tell how they are effective.

Title: Re: Low 1/f noise CMOS amplifier
Post by Frank Wiedmann on Jan 9^th, 2005, 11:35pm

A good overview over auto-zero etc. can be found at http://cmosedu.com/cmos2/designers/Enz%20and%20Temes.pdf.

Title: Re: Low 1/f noise CMOS amplifier
Post by raul on Mar 19^th, 2006, 9:14pm

if you don't want to use any of the sampling techniques and just want to get the low 1/f noise by proper choosing of the devices and architecture, you should:
1. Use a classic two-stage amplifier given that it only contains 4 transistors contributing noise.
2. Use natural/un-implanted devices for your input pair. This helps because the implantation process adds damage to the silicon-oxide interface that creates trapping sites for the carriers in the channel.
3. Use buried channel devices for your input pair. 1/f is noise created at the silicon-oxide interface, buried channel devices have the carriers going below this interface therefore less carriers are trapped and released in Si-O interface and less 1/f noise results.
4. Increase the length of the active load devices in the first stage as much as you can and then sweep the length of the input pair devices as you plot input referred noise at a frequency. The curve will look like a bell and there is an optimum minimum point that you should choose.
5. Maximize the Vgst of your active load devices.
6. Operate you input pair devices in the sub-threshold region(low Vgst) to maximize their gm and minimize input referred voltage noise.

Title: Re: Low 1/f noise CMOS amplifier
Post by xwcwc1234 on Apr 18^th, 2006, 12:46am

How to simulate noise performance of chopping amplifier ? A chopping amplifier with clock can not be simulated using Hspice . is there other tools can do the AC and Noise simulation ?

Title: Re: Low 1/f noise CMOS amplifier
Post by Andrew Beckett on Apr 19^th, 2006, 10:59pm

Do you have access to spectreRF? You could use pss/pnoise analyses to investigate the noise of a chopper-stabilized amplifier,
or pss/pac to look at the frequency response.

Regards,

Andrew.