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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> FFT of a pipelined ADC https://designers-guide.org/forum/YaBB.pl?num=1105866322 Message started by ywguo on Jan 16th, 2005, 1:05am |
Title: FFT of a pipelined ADC Post by ywguo on Jan 16th, 2005, 1:05am Hello, I am testing a 10bit 40MS/s pipelined ADC for undersampling application. It acqures >8bit for analog input < 30MHz. But ENOB (SINAD) decrease fast for analog input > 30MHz. There are many spurs near the fundamental frequency and harmonics on FFT plot for analog input of 35MHz and 45MHz. The FFT plot is shown below. ![]() sorry, it seems that upload picture is not permitted on this forum. Please give me help and welcome any comments. Thanks Yawei |
Title: Re: FFT of a pipelined ADC Post by JJ on Jan 16th, 2005, 12:34pm I think it is normal, because your ADC speed is only 40MSPS. |
Title: Re: FFT of a pipelined ADC Post by John Galt on Jan 17th, 2005, 3:31am You need to respect the Nyquist Sampling Rate or else you are bound to get those spurs (and consequently a bad SNR) For a 40 MSPS ADC your signal band should be less than 20MHz to avoid aliasing. |
Title: Re: FFT of a pipelined ADC Post by ywguo on Jan 17th, 2005, 7:45am Hi, John, Those spurs are not harmonics in FFT plot. That ADC are designed for undersampling application. So I put an SHA precede the pipeline chain. The SHA has much high input bandwidth. Thanks anyway. Yawei |
Title: Re: FFT of a pipelined ADC Post by ywguo on Jan 19th, 2005, 7:51am Hi, I found that is due to poor purity of the analog input signal. I havn't any sinusoid signal generator used for RF. An AWG + some RF filters are the only equipment and accessories I have on hand. When I choose alternative input frequency and filters, the spurs and harmonics are supressed much lower. Thanks Yawei |
Title: Re: FFT of a pipelined ADC Post by codec on Jan 23rd, 2005, 3:02am Hi, Yawei Congratulations!Your circuit is full functional. |
Title: Re: FFT of a pipelined ADC Post by codec on Jan 28th, 2005, 8:40pm Hi, Yawei May I learn the composition of your testing system and types of instruments you are using? I am just going to do my test now. |
Title: Re: FFT of a pipelined ADC Post by ywguo on Jan 30th, 2005, 11:36pm Hi, Codec, My test system and instruments are listed below. Sampling clock -- Agilent 33250A arbitrary waveform generator (poor sine signal, NOT suitable for analog input, but enough for sampling clock) Analog input -- Tektronix AWG520 arbitrary waveform generator (better than Agilent 33250A). It has 10 bit D/A output, so filtering is required for measuring a 10 bit ADC. Recording -- Tektronix TLA715 logic analyzer Power supply -- HP6624 system DC power supply You'd better use band pass filter for both sampling clock and analog input. I used Mini-Circuits SBP and SLP filter. Please go to www.maxim-ic.com. There are many good application notes about high-speed ADC testing. Basically I test my ADC according the method proposed by Maxim. But I don't have so good apparatus as those proposed in Maxim's application notes. I advise you study the evaluation kit of Maxim, like MAX1448 Eval. Kit. Would you please tell me some details of your design? Then perhaps I could give you more suggestions. Good luck! Yawei |
Title: Re: FFT of a pipelined ADC Post by codec on Jan 31st, 2005, 7:29am Thanks, Yawei. I bought 33250A one year ago for arbitray wave generation. However, not only 33250A is poor for SIN wave, but I don't have digitizer either. Currently, we are testing the chip using mixed-signal LSI tester. The circuit we have designed are IPs for custom use in the system. The performance is 10bit 20~60MHz. I will exchange testing result with you after we have got some progress. |
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