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Measurements >> Phase Noise and Jitter Measurements >> Jitter Basics in Ripple Counter
https://designers-guide.org/forum/YaBB.pl?num=1106880836

Message started by Bob on Jan 27^th, 2005, 6:53pm

Title: Jitter Basics in Ripple Counter
Post by Bob on Jan 27^th, 2005, 6:53pm

Hi,

I’m working on PLL jitter simulations with SpectreRF, as guided by Ken Kundert’s paper (Ver. 4b). As a “retread” digital engineer, most of this is new to me, so I very much appreciate the insights provided by this and other papers on your website. The initial task is modeling jitter in the bipolar ECL/CML dividers (input, feedback and output) within a PLL. To begin, a single divide-by-2, D flip-flop (with associated current source bias generators, etc.) was simulated. A 1 GHz differential clock, implemented with complementary voltage pulse sources, drives the flip-flop. An initial current pulse is used to assure quick settling to a digital state. The PSS beat frequency was set to 500 MHz, the number of harmonics was set to 9, and a PSS solution resulted in 3 iterations. The differential positive going, output voltage zero crossing time was plugged into the PNoise analysis (with maximum sidebands set to 9), resulting in a nearly “white” differential output PSD from 1 Hz to 500 MHz. Integrating across this same range (per Eqn. 55 on p. 28) gave a variance of the output noise voltage of 1.077 u. Using the simulated edge rate near 2 V/ns and Eqn. 54 predicts a believable 0.52 ps of jitter. To further check the approach, a circuit with two identical flip-flops in ripple counter mode was simulated. This time the beat frequency and the PNoise “frequency sweep range” were both set to 250 MHz. Integration of the PSD and conversion from noise voltage to jitter gave 0.63 ps, a 21% increase over the single flip-flop case. This seems a long way from the 41% increase projected by the “root of the sum of the squares” thinking of page 28. My questions are –

1. Are these test cases calculated correctly?
2. If so, why are results so different from the “41% increase” expectation?
3. Why do we stop calculating and integrating the PSD at the beat frequency?
4. Does this ignore higher frequency noise that would worsen jitter, or is this issue somehow handled in the “noise folding” (or other) aspect that I don’t understand yet?
5. Could you point me to a resource that explains these issues if it is too complex to answer here?

Many thanks for your help,

Bob

PS: Though it seems unimportant now, I can find no “maxacfreq” parameter to set on the PSS forms. Is this set in some other way? Do I have an old version of SpectreRF? (Affirma Ver. is 4.4.6.100.85)

Title: Re: Jitter Basics in Ripple Counter
Post by Ken Kundert on Jan 27^th, 2005, 11:00pm

Bob,
Here are some quick answers to your questions. Ask for elaborations if these responses are not sufficiently helpful.

First a comment on your measurement. I suspect you are not including enough sidebands. The sidebands are the mechanism by which aliasing is accounted for. If you are not familiar with aliasing, you should study some sampling theory. I recommend you increase the maxsidebands for both measurements. To get the true answer you would need set maxsidebands to infinity, but that would literally take forever. So instead, you want to increase the number enough to get sufficiently accurate answers without going too far, which would slow the simulations. It is difficult to know how many are too many, but it is not that sensitive. If you take a look at http://www.designers-guide.com/Analysis/sc-filters.pdf you will see how the rate at which the compute noise level increases as the value of the maxsideband parameter is increased slows dramatically. So you just have to choose a large enough value for maxsidebands and understand that the computed results will be somewhat of an underestimation.

Basically, the noise in your circuit has some upper bandwidth, and you want to choose maxsidebands high enough so that aliasing from all frequencies up to just above that bandwidth should be included. The frequency of the highest aliased term included is fund*maxsidebands, so roughly
2*noise bandwidth < fund*maxsidebands < 10*noise bandwidth.

Now you probably do not know the noise bandwidth, but it would be the same in both of your circuits. So to get comparable results, you must set maxsidebands twice as large when simulating the second circuit to compensate for the lower fundamental frequency.

So my suggestion is to set maxsidebands to something like 20-40 in the first circuit, and 40-80 in the second. To assure that the results are comparable, set maxsidebands on the second problem to be two times as large as the value used on the first problem.

1. Are these test cases calculated correctly?
maxsidebands must be set as described above.
2. If so, why are results so different from the “41% increase” expectation?
you are only including half the aliasing in the second problem. double maxsidebands.
3. Why do we stop calculating and integrating the PSD at the beat frequency?
the spectrum of sampled data signals is periodic with the period equaling the fundamental frequency (you did use the sampled or time-domain noise feature right?). Integrating over all frequency would result in an infinite energy, which is clearly wrong. Instead you integrate from 0 to the fundamental frequency.
4. Does this ignore higher frequency noise that would worsen jitter, or is this issue somehow handled in the “noise folding” (or other) aspect that I don’t understand yet?
The effect of the higher frequency noise is accounted for with the maxsidebands parameter.
5. Could you point me to a resource that explains these issues if it is too complex to answer here?
Cannot think of any other resources. Maybe others can.

maxacfreq is a parameter of the pss analysis.

-Ken

Title: Re: Jitter Basics in Ripple Counter
Post by Frank Wiedmann on Jan 28^th, 2005, 12:09am

Some more hints:

You can find the maxacfreq parameter by clicking on the Options button at the bottom of the pss setup form.
You should integrate the noise only up to f₀/2 where f₀ is the beat frequency of the pss analysis (see eq. 55). Contributions from higher frequencies will be included in this frequency range through folding if you set the number of sidebands large enough.
Use a logarithmic sweep to correctly resolve 1/f-noise.
Remember to always integrate noise power in V²/Hz, never "noise voltage" in V/sqrt(Hz).
In many applications, the contribution from power supply ripple to jitter is significantly larger than the contribution from device noise.

Title: Re: Jitter Basics in Ripple Counter
Post by Bob on Feb 3^rd, 2005, 2:22pm

Hi Ken & Frank,

Your responses were very helpful and much appreciated! Setting the sidebands to higher numbers and in proper ratio with the fundamental frequency radically improved the results.

To review, 1- and 2-stage ECL/CML ripple counters are simulated with a 1 GHz differential clock while looking for the differential noise/jitter at the outputs. PSS “Beat Frequencies” are now set to 500 MHz and 250 MHz, while PNoise Sidebands are 40 and 80 for the 1- and 2-stage counters respectively. PNoise “Noise Type” is set to “timedomain”, and the zero crossing time observed in the PSS voltage vs. time output is plugged into the PNoise “Add Specific Points” box. The Waveform Calculator is then used to integrate the square of the differential output noise voltage (in V/rt(Hz)) from 1 Hz to the 500 MHz and 250 MHz “Beat” frequencies above. The square root of this result is divided by the observed PSS output slew rate at the zero crossing (differential threshold). The new jitter results are 0.737 ps (1-stage) and 0.985 ps (2-stage) for a ratio of 1.37 … fairly close to the 1.41 ideal. Some of the difference is likely due to non-uniform output loading in the model, and possibly to correlated noise emanating from the common current source bias networks employed. For now, it’s close enough.

Another simulation of the 2-stage counter was performed wherein sidebands were reduced from 80 to 40 to gauge the impact on accuracy. Jitter dropped by about 6.3%, implying a high number of sidebands is needed. (Unfortunately, execution time of the 2-stage, 80 sideband case was about 100 minutes, so efficiency is now a big issue.) New questions include the following:

1. Is the integration range used (~0 to the “Beat Frequency”) correct? Though this seems in line with Ken’s comments and other examples found on the forum, it appears not to match the “fo/2” integration limit of Eqn. 55 and the supporting text, as Frank cautioned in his response.
2. Are there any hard-and-fast rules relating the number of “Harmonics” specified on the PSS form versus the number of PNoise “Sidebands” used? Intuitively, it seems using a low number of “Harmonics” (or a large “strobeperiod” on the PSS Options form) could result in a poor threshold crossing time estimate. Is this true? Are there other issues?
3. One cause of slow execution is my inability to tell PNoise to simulate only one time point. On the PNoise form “Noise Skip Count” is enabled and set to 1000, “Number of Points” is disabled, and one point (the PSS threshold crossing time) is entered into the enabled “Add Specific Points” box. The resultant simulation does two or three time points; they always includes zero, the specified threshold crossing time, and sometimes a third point (2.502 ns for the 2-stage simulation above ?? ). How do I reduce the number of points simulated? Any other tips on reducing execution times?

Thanks again for your help and comments! It’s beginning to make sense to me.

Bob

Title: Re: Jitter Basics in Ripple Counter
Post by Ken Kundert on Feb 3^rd, 2005, 9:46pm

Bob,
1. I was not being precise when I said "integrate to f₀". You should really integrate from 0 to f₀/2 as Frank indicates.
2. The number of harmonics specified on the PSS analysis does not directly affect the accuracy of either the PSS or the pnoise analysis. It only specifies how many harmonics should be calculated for the output. There are no precise rules on how many sidebands you need. However, you need more when the signals change abruptly.
3. Its been a while since I have done this, but I remember simply setting "number of points" to 1. This difficulty will be resolved in an upcoming release.

Concerning the slow speed of the simulations because of the large number of sidebands needed, I recommend that you use the smaller number of sidebands and simply inflate the results by 7%. Once your design stablizes, you can run a final verification with a large number of sidebands to assure you are getting the right results.

-Ken

Title: Re: Jitter Basics in Ripple Counter
Post by Frank Wiedmann on Feb 4^th, 2005, 12:04am

In order to simulate only one time point, select Number of Points, not Noise Skip Count. Enter 0 in the corresponding field. With this setting, only the point(s) entered under Add Specific Points will be simulated.

Depending on your version of SpectreRF, the first time point might be shown as time point 0, additional time points will be shifted by the same amount in this case. This is a bug that has recently been fixed, see http://sourcelink.cadence.com/docs/db/kdb/2004/Oct/11020246.html. The results will still be for the time points you specified, only the time point labels are wrong due to the bug.

Title: Re: Jitter Basics in Ripple Counter
Post by brumby on Oct 31^st, 2005, 6:45pm

Hi,
When I work on Frequency Divider jitter simulation with SpetreRF, as guided by Ken Kundert's paper, and this topics, I find a strange phenomena.

When I simulated a ripple counter, the frequency of input is set to be 2.5GHz.
The var(nv(tc))=(3.253mV)^2 in the divided-by-2 frequency divider, and the slope of output signal at time tc is 20GV/s.

When another divided-by-2 frequency divider is cascaded, and this means the new frequency divider is divided-by-4. The input frequency is set to be 2.5 GHz, too. The slope of output signal are almost same as last one, but var(nv(tc)) is changed to be (0.363mV)^2.

In the first simulation, beat frequency is set to be 1.25 GHz, and maxsidebands is set to be 30. var(nv(tc)) is integrated from 1 Hz to 625MHz.

In the second simulation, beat frequency is set to be 625MHz, and maxsideband is set to be 60. var(nv(tc)) is integrated from 1Hz to 312.5MHz.

Where I am wrong?

Thanks

Title: Re: Jitter Basics in Ripple Counter
Post by Ken Kundert on Oct 31^st, 2005, 7:42pm

Did you increase maxsidebands?

-Ken