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Design Languages >> Verilog-AMS >> syntax problem A <= #'B C;
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Message started by MARCE on Feb 23^rd, 2005, 4:48am

Title: syntax problem A <= #'B C;
Post by MARCE on Feb 23^rd, 2005, 4:48am

Hallo everybody,
can anyone help me?
I need to know what's the meaning of the following expression

A <= #'B C;

(A,B and C are 3 different clocks)

Thanks

Marce

Title: Re: syntax problem A <= #'B C;
Post by Geoffrey_Coram on Jun 6^th, 2005, 8:43am

This isn't really an AMS question; look in your 1364 Verilog reference.
The "<=" construct is a non-blocking assignment, but usually you see something like

Code:

A <= #10 1;
B <= #5 0;

With the non-blocking assignment, B gets the value 0 at time 5, rather than time 15 if a regular assignment had been used. I've never seen a delay specified as 'B as in your example, rather than as a number. The LRM allows a number or an identifier, not an expression like 'B.

Title: Re: syntax problem A <= #'B C;
Post by jbdavid on Aug 3^rd, 2006, 6:21am

if there is a
`define B 12 somewhere.. then
#`B would expand to
#12
B may be a clock but `B is a just a macro that could be ANYTHINg..
jbd