The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Measurements >> Phase Noise and Jitter Measurements >> Basic question regarding pll noise modelling
https://designers-guide.org/forum/YaBB.pl?num=1109234769

Message started by bhaijiamit on Feb 24^th, 2005, 12:46am

Title: Basic question regarding pll noise modelling
Post by bhaijiamit on Feb 24^th, 2005, 12:46am

I have following question regarding the voltage domain model to simulate the long term jitter for PLL.

1)Do we need to do any processing on the phase noise no. obtained from vco pnoise sim (like div by 2 to remove amplitude noise) to calculate the jitter no. for vco verilog model.
1) In the vco model why we need to multiply the jitter no by sqrt(2) when we are updating the jitter on both edges. (actually my verilog models are showing the ltj sigma sqrt(2) time more then my matamatica models)
2) What difference will it make if i update the jitter only on rising edge only and remove the multiplication factor of sqrt(2)
3) In the matlab script where exactly the multiplication factor of bin is taken care.
In order to avoid the scaling of resolution bandwidth, i changed the script there i multiplied the Sphi by T. Is it correct.
4) Can we take care of charge pump current noise by adding the random current source with sigma of integrated current noise at the control voltage node of pll.
5) Similarly can be add loop filter noise by adding random gaussian voltage noise with sigma of sqrt(kt/c).

Regards
-Amit