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Simulators >> Circuit Simulators >> The Pwl file is empty.
https://designers-guide.org/forum/YaBB.pl?num=1109780639

Message started by kamesh419 on Mar 2^nd, 2005, 8:23am

Title: The Pwl file is empty.
Post by kamesh419 on Mar 2^nd, 2005, 8:23am

Dear all,

I have modified many things compared to my last post. That is the reason i am posting a new thread.

The schematic that iam working on now is

http://www.cyd.liu.se/users/~kamva881/temp/circuit.jpg

I tried to simulate it. It gives me an error saying (This is a part of my output.log file)

Quote:

Simulating `raw/tb_DW01_add_cla_width8' on MYHOSTMACHINE at 4:45:30 PM, Wed Mar 2, 2005.

Notice from spectre during hierarchy flattening.
timeSweep: `stop' has the unusually large value of 100 s.
Error found by spectre during initial setup.
Waveform file
`/home/coworker/kameswar/glitches/SIMULATION/CADENCE/pwlFile5' is
empty.

spectre completes with 1 error, 0 warnings, and 1 notice.
spectre terminated prematurely due to fatal error.

But my pwlFile5 is not empty. a part of my pwlFile5 is as follows.

Quote:

v_B1 B<1> 0 pwl '0*(10n)' '3'
+, '0*(10n)+.3n' '3', '1*(10n)' '3'
+, '1*(10n)+.3n' '0', '2*(10n)' '0'
+, '2*(10n)+.3n' '0', '3*(10n)' '0'
+, '3*(10n)+.3n' '3', '4*(10n)' '3'
+, '4*(10n)+.3n' '0', '5*(10n)' '0'
+, '5*(10n)+.3n' '0', '6*(10n)' '0'
+, '6*(10n)+.3n' '0', '7*(10n)' '0'
+, '7*(10n)+.3n' '0', '8*(10n)' '0' ... ...... ... ..

I do not understand where the problem is. every thing that i do depends on this small test circuit which iam developing now. Plz help me.

Thanks in advance,
kamesh.

Title: Re: The Pwl file is empty.
Post by Ken Kundert on Mar 2^nd, 2005, 9:41am

What you included in your waveform file is a netlist description of a PWL waveform. What Spectre expects in a waveform file is simple time-value pairs, and they must consist of simple numbers, not expressions. Thus, the file should contain something like the following.

0 3
10e-9 3
10.3e-9 0
20e-9 0
...

-Ken

Title: Re: The Pwl file is empty.
Post by kamesh419 on Mar 2^nd, 2005, 10:14am

Thank you ken for the reply.

I know that your suggestion works. by using your method i get the digital wave form and not the analog one i believe. Modelling a digital waveform can also be done by using a simple verilog testbench instead of using vpwlf sources. But the problem is i cannot model the transitions from 1-->0 and from 0-->1, like using raising and falling times.

Can i make use of my netlist description of PWL waveform in any way so that i get the analog description of a wave and not a digital one ? or can i use your method to do this in any different way ?

Thanks in advance,
kamesh.

Title: Re: The Pwl file is empty.
Post by Ken Kundert on Mar 2^nd, 2005, 10:14pm

The waveform I showed is a PWL waveform, so it does transition smoothly between specified values. In this case it takes 300ps to transition between levels.

-Ken