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Simulators >> Circuit Simulators >> how to scale OPUS schematic
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Message started by blam on Mar 7^th, 2005, 3:58pm

Title: how to scale OPUS schematic
Post by blam on Mar 7^th, 2005, 3:58pm

Hello Cadence Experts,

We do customer design for microprocessors. Everytime we adopt a new technology, we use the original schematic with old micron size and set a scaling factor in spice netlist to do circuit simulation for the new technology.

But for some reasons, we need to convert the micron size in original OPUS schematics to real micron size. This is just a multiplication factor on W and L of transistors. Since the schematics are large and involve many cells, the conversion cannot be done by hand. Does anyone have experience of doing this kind of conversion on Cadence OPUS schematic? Your input are well appreciated.

-Bill