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Design >> Mixed-Signal Design >> How to simulate DAC performance?
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Message started by Leyman on Mar 13^th, 2005, 7:57pm

Title: How to simulate DAC performance?
Post by Leyman on Mar 13^th, 2005, 7:57pm

Hi everyone!

How to simulate for DAC performance i.e. INL, DNL, Gain Error, Offset Error etc.

What kind of EDA toold do I need for this? Can I simulate using HSpice?

Really appreciate if someone can help!..CHEERS :)

Title: Re: How to simulate DAC performance?
Post by sheldon on Mar 30^th, 2005, 10:51pm

Leyman,

There are examples of how to implement the INL
and DNL tests for D/A Converters in the Cadence ICXX
ahdlLib. The models default to 8 bits, but internally
the number of bits is parameterized and easily modified.
Calculating the gain and offset error should be fairly
straightforward. Simulate the transfer function (zero
scale and full scale output) then use the Calculator to
simulate the slope[gain] and crossing point[offset]. In
the past, I have used Spectre for simulating D/A
Converters both at the behavioral and transistor level.

One final comment, simulating D/A Converter dynamic
performance is more of a challenge. If you use testbenches
that are appropriate for A/D Converters, then the DAC
output will look like a "picket fence", that is, the noise
in the spectrum is concentrated at the tones of the
beat frequency so measuring Spurious Free Dynamic
Range is difficult.

Best Regards,

Art Schaldenbrand