The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Multi-phase detector in CDR circuit; Not half rate https://designers-guide.org/forum/YaBB.pl?num=1110920151 Message started by raymond_luo2003 on Mar 15th, 2005, 12:55pm |
Title: Multi-phase detector in CDR circuit; Not half rate Post by raymond_luo2003 on Mar 15th, 2005, 12:55pm Dear all, Recently I got a task to design a SerDes with around 1GHz data rate. The tranmitter got a 100MHz local clock, and the the receiver got a similar but with a slight difference local clock, say 99.99MHz. So I have to use a CDR in my receiver to extract the clock information from the embeded 8B/10B encoded serialized 1GHZ data stream. SO my CDR will first use the local 99.99MHz as a clock reference, and I will need a Phase Dector to track the phase information of the serialized data stream. Since I will use a CDR with multi-phase VCO, I am not sure the number of phases of that VCO, it could be 10 or 5. I read a lot of papers, I didn't find any suitable phase detector for a 5 phase or 10 phases. I can see some papers with full rate or half rate phase detector from Razavi. Anyone got relevant experience? Or should I generate a 1 GHz clock and use a full rate phase detector? Thanks in advance, Raymond |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by Paul on Mar 15th, 2005, 1:09pm Raymond, I believe that you want to combine your sub-rate phase-detector directly with the SerDes function, don't you? For relatively obvious reasons (notice you did it in your SerDes question), sub-rate CDRs are usually built with 2^n ratio between incoming data and receive clock frequency. Look for more papers by Razavi, his students are frequently using sub-rate CDRs. E.g.: "A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology", JSSC December 2003 which describes a quarter-rate CDR. For this reason, I would suggest you use 4 or 8 clock phases, not 5 or 10. The choice between half-rate and full-rate designs strongly depends on your application. If you have to deserialize your incoming data anyway, it makes sense to combine the CDR and Des parts using sub-rate architectures. From your explanations it is not clear to me whether you have a local clock at 100MHz available or whether you want to generate it from a VCO inside a CDR PLL. If you already have a clean clock available, using a phase-interpolation based solution or something like that may be a good solution, it avoids having one more oscillator on the same die. But it is hard to give advice without having the whole picture. Good luck Paul |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by raymond_luo2003 on Mar 16th, 2005, 1:50am Dear Paul, Thank you indeed. I 'd like to explain my system clear. I have to build a 1GHz data rate SerDes in one chip. And I have a 100Mhz+/-100ppm local reference x'tal clock on this chip. Obviously, the 10:1 ratio is due to 8B/10B encoder on chip for DC balance. TX structure. 8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> Serializer ==> 1 Bit @1GHz I will use a PLL to generte the evenly spaced 10 phases of 100MHz clock which will serve the clock source for the serializer. RX structure, RX is receiving the 8B/10B coded data stream from another similar SerDes chip with embeded clock and slightly different frequency , say, 100MHz+/- 200ppm. Since the local clock 100MHz+/-100ppm is different from in coming embeded clock, I will have to use a CDR to recover the clock from data with embeded clock. 1 bit @ 1GHz+/- 200ppm ==> CDR ==> 10 bit@ 100 Mhz +/- 200ppm PLUS 10 phases 100MHz +/- 200ppm That's why I hope to have a sub-rate phase detector, say, 5 phases for the CDR. If we use the quadrate phase detector for CDR, I will modify the SerDes entirely, especially at clock domain. NEW TX structure 8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> 10B/8B converter ==> 8 bit @ 125MHz==> Serializer ==> 1 Bit @1GHz So will have to generate the 8 phases 125MHz from local reference clock. NEW RX structure 1 bit @ 1GHz+/- 200ppm ==> CDR ==> 8 bit@ 125 Mhz +/- 200ppm PLUS 8 phases 125MHz +/- 200ppm ==> 8B/10B converter==> 10 bit@ 100 Mhz +/- 200ppm PLUS 1 phase 100MHz +/- 200ppm from addtional PLL. It seems more work to me comparing with the previous structure, that 's why I am seeking the 5 or 10 phase sub-rate phase detector One more question, how about the frequency locking range of normal CDR phase detector, say 1%? Or less than 1 %? Please advise, Thanks in deed! Raymond |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by Paul on Mar 16th, 2005, 3:02am Raymond, OK for your explanations. Regarding the SerDes, I would be interested to learn why you want to use multi-phase clocks from a PLL instead of generating a 1GHz clock. In most current technologies you should be able to generate a 1GHz clock. I agree that the new structure has some overhead. But I also think (unlike what I said in yesterday's post) that you should relatively easily be able to use a 10-FF phase detector. I believe the PD topology presented in the sub-mentioned paper would work with 10 phases instead of 8. In the RX, don't forget to put an elastic buffer between your CDR and your system clock domain. Somehow you have to absorb the +/- 200ppm variations. Paul |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by raymond_luo2003 on Mar 16th, 2005, 3:49am Dear Paul, I agree with you. I am considering two types SerDes for this 1GHz test chips now;One for the 1GHz single clock version for both serializer and deserailizer. The other, as you suggested, it seem feasible to design a 10-phase phase detector instead of 8 if I slightly modify the structure from Razavi's proposal, so that I can directly use the multi-phase sub rate phase detector. In order to co-operate with the scability for future, since my SerDes will have the mission to support 3.2GHz in future, probably the multi-phase solution is more attractive to me. I just wander, there seems almost every SerDes got 8B/10B encoder in high speed link or optical link, why there is no particular paper mentioning about the 10-phase sub rate phase detector instead of 2^n sub-rate phase detector? Is that so easy that no value to mention it? Or I am a little stupid to keep asking stupid question while this is quite apparent for other people. It really put me in puzzle. Anyway thank you, it seem quite clear now for the architechiture. By the way, regarding on the Bang-Bang type and Linear type phase detector, which one is better? I am quite confused by this as well. It seem bang bang type got large jitter, but with inherent retime data output. Linear type phase detector have better jitter performance while it suffer from the data-clock skew which reduce the time margin. Even in Razavi's half rate phase detector, one paper in 2001 adopt the linear type PD, at year 2003, another paper they adopt a Bang-Bang type half rate PD. Both seems to serve same application 10Gbs CDR. Any advise? Best Regards, Raymond |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by Paul on Mar 16th, 2005, 5:37am Raymond, I am not an expert on the SerDes issue, but as far as I understand, 8b/10b encoding is usual in short-distance communications (Gb-Ethernet, Firewire, Fibre Channel, etc...), but not in long-haul systems like SONET/SDH. Many papers still focus on the second application, which is more stringent in terms of jitter specifications, although I believe the market is shifting to short-distance applications. That may be a reason why little publications show structures including encoding/decoding. I don't know what technology you are using, but if you want to go up to 3 Gb/s, I would not implement the first receiver with 10 phases at 100MHz. The first reason is that you will hardly find a XTAL reference oscillator above 150MHz, the second is that at 100MHz/1GHz you may miss some issues arising at higher frequencies. Why don't you go for the 3 Gig design directly and take more time (and possibly one more design integration) for it (this is my personal opinion, some people may disagree)? Concerning the linear/binary detector choice, I don't think there is a better or a worse solution. I believe it depends on what architecture people are used to and somewhat on the application requirements. Good performance has been shown with both designs. Maybe (some pretend) the binary detector could be more suitable to go to the maximum data rates the technology can support. BTW, Razavi even has a comparison paper with the two 10 Gb/s designs. Paul |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by ywguo on Mar 17th, 2005, 10:57pm Luo, It looks that you are working on 1.25G Serdes compatible with 1000Base-X and 4 channel 3.125G Serdes in the future. Is that right? I agree with Paul. Just give up the sub-rate CDR with 5 or 10 clock phase. You could choose half-rate CDR or full-rate CDR. As the 8b/10b encoder and decoder, it is easy to design and synopsys provide them in design ware. So it is rarely described in IEEE jounals and transactions. Best regards, Yawei |
Title: Re: Multi-phase detector in CDR circuit; Not half Post by neoflash on Nov 11th, 2005, 7:09am ywguo wrote on Mar 17th, 2005, 10:57pm:
The poster's spirit of innovation should be encouraged. However, there is challenging to use complicated PD. Control of clock phase will be terrible. 3.125G does not sound high. You will be able to design half-rate CDR very, very easily in 130nm process. |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |