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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Testbenb for PLL Phase Noise Simulation https://designers-guide.org/forum/YaBB.pl?num=1111004152 Message started by jfosorio on Mar 16th, 2005, 12:15pm |
Title: Testbenb for PLL Phase Noise Simulation Post by jfosorio on Mar 16th, 2005, 12:15pm Hi everybody, I am trying to perform phase noise simulations using the code source founded in the article: "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers", in the phase domain (actually what I like to do is to perform it in the jitter domain but I found easier to start by the phase). With some little changes all the modules work O.K. But I have problems once the design has been elaborated and spectre start its job. I am almost sure that the problem is the iprobe instance necessary in the noise command in spectre, I don’t know how to have a correct iprobe instance to the noise instruction. Can anybody suggest me a test bench for this design?. I have attached the testbech I am using now and the error messages I got as well as the top level file. Thanks in advance. Felipe * test bench Spectre file noise ( out gnd ) noise start=1M stop=100M iprobe=OSC * Error Message Analog Kernel using -ANALOGCONTROL run.scs. Error found by spectre during hierarchy flattening. noise: Invalid component name `OSC' was given as value of parameter `iprobe'. Ignored. name conflict: value `OSC' of type `scalar string' encountered. Expected value is of type `scalar instance'. noise: Terminals are not distinct. * Top module `include "disciplines.vams" `include "phase.vams" module pll(out); output out; phase out; parameter integer m = 1 from [1:inf); // input divide ratio parameter real Kdet = 1 from (0:inf); // phase detector gain parameter real Kvco = 1 from (0:inf); // VCO gain parameter real c1 = 1n from (0:inf); // Loop filter C1 parameter real c2 = 200p from (0:inf); // Loop filter C2 parameter real r = 10K from (0:inf); // Loop filter R parameter integer n = 1 from [1:inf); // feedback divide ratio phase in, ref, fb; electrical c; oscillator OSC(in); divider #(.ratio(m)) FDm(in, ref); phaseDetector #(.gain(Kdet)) PD(ref, fb, c); loopFilter #(.c1(c1), .c2(c2), .r(r)) LF(c,gnd); vco #(.gain(Kvco)) VCO(c, out); divider #(.ratio(n)) FDn(out, fb); endmodule |
Title: Re: Testbenb for PLL Phase Noise Simulation Post by Ken Kundert on Mar 16th, 2005, 1:50pm You don't really need the iprobe unless you want input referred noise. In this case, you must replace OSC with a dc vsource. -Ken |
Title: Re: Testbenb for PLL Phase Noise Simulation Post by jnvnd on Oct 16th, 2008, 4:25am Hi, I am using the same methodology, but not able to get the results, can you share your test bench? |
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