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Design >> Mixed-Signal Design >> Different Process Technologies on Single Chip
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Message started by Vishwanath M on Apr 4^th, 2005, 1:48am

Title: Different Process Technologies on Single Chip
Post by Vishwanath M on Apr 4^th, 2005, 1:48am

Hi Friends,
I have one query, Can I have different Process technologies like 0.18um, 0.13um, say for example OpAmp I will place half transistors with 0.18um and remaining with 0.13um. Is it possible to fabricate?

Thanks in Advance....

Regards
Vishwanath M

Title: Re: Different Process Technologies on Single Chip
Post by DReynolds on Apr 4^th, 2005, 6:03am

Vishwanath, the short answer is no, you can't have different processes on a chip, however, you can of course draw a .18um transistor on a .13um design. Another exception is that most fine line processes have dual gate oxides ( a thin one for regular circuits, and a thicker one for IO) in this case you really can have two different devices like .13um and .35um(3.3v) on a chip.

hope this helps

David Reynolds

Title: Re: Different Process Technologies on Single Chip
Post by Vishwanath M on Apr 6^th, 2005, 3:25am

Hi David Reynolds,
If we can have 0.13um for core logic (thin oxide) and 0.35um for I/O Pads (Thick Oxide) on a chip. Why can't have two process technologies.
If not! is it fab problem or other problem..

Other view...
From simulations point of view we can do using two process technologies using spectre.
After this, face problem arise to do extraction/LVS....
Is it true what I am saying....

Thanks for your replay....
Vishwanath M

Title: Re: Different Process Technologies on Single Chip
Post by Paul on Apr 6^th, 2005, 5:44am

Vishwanath,

I am not sure to understand you correctly. It is not possible to use different manufacturing processes on a single wafer because there is very little need. As in 0.13um technology you can draw your device's channel length whatever you want, provided it is larger than 0.13um, I don't see the reason why you would like to have 0.18um technology devices...

The reason to provide "0.35um devices", which have thicker gate oxyde, is to have convenient voltage levels to communicate with the outer world. Applying the 3.3V I/O voltage to 0.13um devices would break down the gate oxyde very quickly.

Could you share the reasoning behind your question, please?

Paul

Title: Re: Different Process Technologies on Single Chip
Post by Vishwanath M on May 2^nd, 2005, 12:18am

It is only knowladge....
Thanks Paul...