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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Phase/Frequency Detector https://designers-guide.org/forum/YaBB.pl?num=1114434532 Message started by Fei on Apr 25th, 2005, 6:08am |
Title: Phase/Frequency Detector Post by Fei on Apr 25th, 2005, 6:08am I implemented a PFD using TSMC 0.18 um lib model. The design is proposed in Razavi's book "RF micronelectronics", which is composed of four Nor gates in each D flip flop. The interesting thing about the PFD is that it is sensitive to the initial states of the circuit. For example, the output can be different for the same delay between reference clock and VCO clock if the set of initial states of the two DFF is changed. I check the DC solutions of the circuit. It has a metastable state, which means that the output is neither 0 nor Vdd. Does it cause the problem? Any comments on it are welcome. Thanks Fei |
Title: Re: Phase/Frequency Detector Post by jfyan on Apr 25th, 2005, 7:51am hi fei: i met the similar thing as you stated, but the outputs (v(up) and v(dn) ) are sensive the some gates's sizes. please check the signal reset and v(ref) and v(vco), whether a missing clock eage is happened. for more information about nonideal linear PFD characteristic, please refer to Mozhgan Mansuri's phd thesis. (she is a phd of UCLA), you also can find her jssc paper in ieee. ps: who can tell me how can i simulate the dead zone of PFD, and how much dead zone can i ignore, and has no serious effect in jitter characterictic . thanks advance. |
Title: Re: Phase/Frequency Detector Post by vijay on Oct 25th, 2005, 4:15am The dead zone of the PFD along with the charge pump is what you are looking for?? |
Title: Re: Phase/Frequency Detector Post by Ken Kundert on Oct 25th, 2005, 10:42am In general the metastable state is not a problem. All flip-flops and latches have them. In general they are unstable equilibrium points, so they are never reached in practice. -Ken |
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