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Design Languages >> Verilog-AMS >> How to model a divider with multiphase output?
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Message started by wchlee on May 10^th, 2005, 6:26am

Title: How to model a divider with multiphase output?
Post by wchlee on May 10^th, 2005, 6:26am

Hello!

I'm trying to build a frequency divider that can generate multiphase output. i.e., 0,90,180,270 in quadrature...
but I have no idea how to achieve the desired phase shift?
Also the examples in designer's guide website are mostly square wave output, is it possible to have a sine wave output?

best regards,

Title: Re: How to model a divider with multiphase output?
Post by jbdavid on Aug 3^rd, 2006, 6:29am

Probably too late for your question.. and this Probably belongs in the Modeling section not the language section..

1. typically multiphase dividers use multiple FF,
your could actually create two divide by two circuits and run on off the regular signal and the other off the inverted clock..
If your flop has Q Qb outputs you're done.

Since its a clocked effect, I wouldn't offer sinusoidal ,but you could use an RC filter (Rout, Cload+Cwire) on your outputs
to get something close to sinusoidal..(reduce the energy of the high frequency parts.. )
jbd