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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Simulating ADC INL, DNL and FFT Spectrum https://designers-guide.org/forum/YaBB.pl?num=1117724219 Message started by Sid on Jun 2nd, 2005, 7:56am |
Title: Simulating ADC INL, DNL and FFT Spectrum Post by Sid on Jun 2nd, 2005, 7:56am Hi, I have built a 12-bit ADC in Cadence. So far I have been simulating it with a ramp input and checking that the codes increase monotonically at the speed of interest. However, even for checking about 30 continuous codes the simulation takes 12 hrs due to the large size of the pipeline ADC. How do I simulate it's INL, DNL and FFT spectrum within a reasonable simulation time? Any help will be greatly appreciated. Thanks, Sid |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by sheldon on Jun 2nd, 2005, 8:53pm Sid, Could you provide some details about your circuit and simulation setup? For example, does the simulation include back-annotated parasitics? Power supply parasitics? etc? My expectation is that a for a circuit level simulation of a 256 point FFT for a 10bit Pipeline ADC should take about 6 hours on good harware, Opteron. For older hardware SUN UltraSPARC, the time will be closer to 20 hours. If you setup the simulation correctly, you should be able to get ~100dB of dynamic range, for a 0dB input the FFT noise floor should be down at -100dB. This should be enough sufficient for most 10-12 ADCs. INL and DNL are really tough to simulate since you need to exercise each bit several times. One strategy is to run the FFT simulation at a low input frequency an calculate the INL from the SFDR. Best Regards, Sheldon |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by ywguo on Jun 2nd, 2005, 11:46pm Sheldon, I am interested in the method that you mentioned to measure INL. Quote:
Would you please explain it in detail? How much points does it need to calculate INL from the SFDR? Thanks Yawei |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by sheldon on Jun 5th, 2005, 6:33pm Yawei, There is a short summary at : www.stanford.edu/class/ ee315/handouts/h05_lecture3_2.pdf see page 35. Let me know if you need more detail, I have more other references. Best Regards, Sheldon |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by Leyman on Jun 30th, 2005, 8:47pm Sheldon, I could not get the document from stanford website regarding simulation INL/DNL? Do you mind sharing the documents? Any other good reading material on INL/DNL simulation? You can sent the document to: snoop835@hotmail.com Thank you in advance -leyman- |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by jbdavid on Oct 3rd, 2005, 11:14pm I also addressed that in my tutorial on Pipeline converters on the 2002 BMAS www.bmas-conf.org along with a number of paper references back to the classic papers that outline that methodology for testing ADC's.. jbd |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by Sid on Oct 4th, 2005, 8:20am David, Exact paper name please? Thanks, Sid |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by sheldon on Oct 4th, 2005, 6:42pm Greetings, Please look at the following paper, " FFT test pf A/D Converters to Determine the Integral Nonlinearity", Francesco Adamo, et. al., Transactions on Instrumentation and Measurement technology, Vol 51. No 5., October 2002, page 1050-1054 Best Regards, Sheldon |
Title: Re: Simulating ADC INL, DNL and FFT Spectrum Post by jbdavid on Oct 5th, 2005, 4:59pm Maybe I shouldn't wait for David to answer since the question seemed to be for me ::) http://www.bmas-conf.org/2002/index.html Look for: Modeling and Test Bench Generation: A Case Study with Pipelined A/D Converters (paper 630KB) Jonathan David ― Cadence Design Systems, USA HTH jbdavid |
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