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Measurements >> Phase Noise and Jitter Measurements >> a question on PLL simulation
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Message started by James on Jul 12^th, 2005, 4:32pm

Title: a question on PLL simulation
Post by James on Jul 12^th, 2005, 4:32pm

Dear all,

When I simulate the transistor level PLL in spectre, I found the following problem which annoyied me for two weeks.
My PLL can lock the reference frequency but cannot lock the reference phase. The input reference frequency is 25MHz. The output clock of the divider has the same frequency but with rising(or falling) edges 650ps away from that of the reference clock. Is that accecptable? The VCO is working at 200M.

What's more, when I only simulate the VCO. I found the control voltage need 2.3V to let the VCO oscillate at 200MHz. But when I simulate the whole PLL, after the PLL is stable, the control voltage is only 1.8 V. Why?

Thanks a lot

Title: Re: a question on PLL simulation
Post by Andrew Beckett on Jul 12^th, 2005, 9:27pm

I'd have thought only you can say whether that is acceptable!

As for the change in the control voltage - might this be due to some loading effect on the VCO altering the gain of the VCO? If you simulate the VCO with whatever the VCO is loaded by (the divider, presumably), do you see the same effect?

Regards,

Andrew.

Title: Re: a question on PLL simulation
Post by sheldon on Jul 12^th, 2005, 10:34pm

James,

A few other questions how are you defining frequency lock? Is the
control voltage constant? Do you see reference feedthrough on the
control line? Finally maybe this is reaching, but what are the loop gain
and phase at 25MHz? If you think about an op-amp, the loop gain rolls
off at frequency, so the offset voltage due to gain error increases. It
maybe that the finite loop gain is resulting in the phase error you see,
that is, when the loop gain is infinity the phase error is zero and as
loop gain decreases the phase error increases. If you use different
divider ratios (and reference frequencies) how does the phase error
change?

Best Regards,

Sheldon

Title: Re: a question on PLL simulation
Post by James on Jul 13^th, 2005, 8:18am

Andrew,

you are right, I broke the loop and simulate the VCO control voltage vs. output frequency. It's consistent with the close loop result.

Sheldon,

I watch the control voltage to tell if the PLL is locked. After the control voltage is flat, I think it's locked. But even the Vcontrol is flat, when I zoom in it to watch closely, there is small ripple, around 1.5mV.

I am also curious about how to simulate the loop gain of the whole PLL, the capture rang and the lock range. I read the cdsdoc about the pllLib in Cadence, but have no idea how to apply it to my PLL. Is there any way I can get these information by simulating on transistor level?

For loop gain, I get it by using a software of "PLL Design Assistant" written by a professor in MIT. I found my loop gain is 1.128e13. In the software simulation, it indicates increasing divider ratio will decrease the loop gain. I will simulate it in the transistor level.

But I found an interesting fact. When I only simulate the PFD+CP+loop filter, if I add two identical pulse source in the inputs of PFD, in theory, the output of Charege Pump should be constant, thant means whent the control voltage should be constant after the inputs of PFD are identical. But the simulation shows the CP output go up. That means even the reference clock and the output clock are exactly same, the control voltage of VCO cannot be constant. I think this fact can explain why the PLL need a phase error to keep the Vcontrol be constant. If I change the ratios of the pmos and nmos switches in CP, the CP output can go down or still go up but by a different slope. If I change the current sink in CP, I also can watch the same effect on CP output. I cannot understand this result.I am confused.

Best

Title: Re: a question on PLL simulation
Post by rf-design on Jul 13^th, 2005, 11:03pm

If you offset REF and DIV signal input to the PFD by the 650ps observed in the close loop, is the filter output stable then?

If the UP and DN current sources mismatch by 20% and the minimum active time of the PFD is 650ps/0.2=3250ps you will get a equivalent time offset of 650ps.

Please plot the I(CHP) over T(UP vs. DN) to know the transfer function of the PFD-CHP chain. You then also have informations about the linearity.