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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> Error Message in NCSIM https://designers-guide.org/forum/YaBB.pl?num=1121451389 Message started by Boon-Siang on Jul 15th, 2005, 11:16am |
Title: Error Message in NCSIM Post by Boon-Siang on Jul 15th, 2005, 11:16am Hi, I'm fairly new to AMS Design Environment. I wanted to simulate an schematic in AMS environment. I had written the Ideal ADC, signal generator and a clock generator in Verilog AMS and I want to test it with my compensation filter (designed with schematic). I had created symbols and connected them. I created a config for the test circuit and ran Cadence Hierachy Editor. The AMS Design Prep compile my design without errors and created the correct netlist. Then I tried to run simulation to invoke NCSIM. NCSIM was invoked correctly but had an error message which prevents me from simulating. The following are the error messages: --------------------------------------------------- Updating snapshot thesis.inv_ams:ams1121398730741 (SSS), reason: mixed-signal design Update of snapshot thesis.inv_ams:ams1121398730741 (SSS) successful. Starting analog simulation engine... libpalermo: @(#)$CDS: libpalermo version 02/26/2004 03:08 (ncss17) $(sub-version 0226 ) Analog Kernel using -ANALOGCONTROL /nfs/ecsnas1/users/eegrad/bcheah/ibm13/sch.scs. Error found by spectre during circuit read-in. inv_ams: Parameter expression for `ngcon' is not supported. spectre terminated prematurely due to fatal error. ncsim: *E,RNAERR: Simulation is complete, analog initialization error. --------------------------------------------------- I'm guessing it's a setting for spectre within some hidden file or something which is wrong. I tried it in some other account and it works. Thus I'm dumbfounded now. If anyone could point me to the right direction, please help. Thank you very much. Boon-Siang |
Title: Re: Error Message in NCSIM Post by sheldon on Jul 16th, 2005, 7:59am Boon-siang, Have you tried using nchelp? If I remember the syntax it is nchelp ncsim RNAERR from the command line. Nchelp usually provides a pretty good explanation of the problem. Best Regards, Sheldon |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 16th, 2005, 4:17pm Sheldon, Thank you very much for your reply. I had already solved that problem. It happen because I uses global sources (vdd! & vss!) in my schematics. After changing it, it works fine. I tried your suggestion using the nchelp but I don't think it's that helpful. Below is what it gave me: ----------------------------------------------------- [chip5]>nchelp ncsim RNAERR nchelp: 04.10-s025: (c) Copyright 1995-2004 Cadence Design Systems, Inc. ncsim/RNAERR = The analog simulator detected an unrecoverable error condition during run-time initialization. Simulation cannot proceed. ---------------------------------------------------- Thank you very much for your help. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 16th, 2005, 4:30pm Sheldon or anyone who is able to help, After fixing that error, another problem came around. After running DesignPrep to get my design's verilog netlist. I noticed that there's something wrong with it. I have tried it on 2 accounts. One of the account works and the other doesn't because both account generated a slightly different verilog netlist. I had tried searching for any misconfiguration and tried copying the settings of the account that works to the one that doesn't but still with no prevail. Below is a verilog netlist generated from the NON-WORKING account: ---------------------------------------------------- // Verilog-AMS netlist generated by the AMS netlister, version 5.0.33.500.3.31. // Cadence Design Systems, Inc. `include "disciplines.vams" module inv_ams ( Vout,vss,vdd,Vin ); output Vout; inout vss; inout vdd; input Vin; nfet #(.panw8(0p), .panw6(0p), .ps(1.525u), .panw10(0p), .plnest(-1), .pam2(0p), .panw2(0p), .plorient(-1), .nrs(1.1064), .panw9(0p), .nrd(1.1064), .as(1.24E-13), .l(160.0n), .rf(0), .panw5(0p), .panw7(0p), .pld200(-1), .pd(1.525u), .panw3(0p), .dtemp(0), .pam1(0p), .nf(1), .ad(1.24E-13), .ngcon("1"), .rf_rsub(1), .panw4(0p), .w(280.0n), .panw1(0p), .m(1)) (* integer library_binding = "cmrf8sf"; integer passed_mfactor = "m"; *) T1 ( Vout, Vin, vss, vss ); pfet #(.panw8(0p), .panw6(0p), .ps(2.715u), .panw10(0p), .plnest(-1), .pam2(0p), .panw2(0p), .plorient(-1), .nrs(1.1064), .panw9(0p), .nrd(1.1064), .as(2.09E-13), .l(160.0n), .rf(0), .panw5(0p), .panw7(0p), .pld200(-1), .pd(2.715u), .panw3(0p), .dtemp(0), .pam1(0p), .nf(3), .ad(2.09E-13), .ngcon("1"), .rf_rsub(1), .panw4(0p), .w(280.0n), .panw1(0p), .m(1)) (* integer library_binding = "cmrf8sf"; integer passed_mfactor = "m"; *) T0 ( Vout, Vin, vdd, vdd ); endmodule ---------------------------------------------------- If you noticed the ngcon (number of gate contacts) in both pfet and nfet is ngcon("1") but from the WORKING account it's ngcon(1). Hence, I manually removed the "" in the NON-WORKING account and I could invoke AMS simulator succefully. But, I cannot do this for all my design, it would be impossible. Anyone out there who can help me?? The error that I'm getting if I don't manually remove the quotations are shown below: ---------------------------------------------------- Updating snapshot thesis.inv_ams:ams1121398730741 (SSS), reason: mixed-signal design Update of snapshot thesis.inv_ams:ams1121398730741 (SSS) successful. Starting analog simulation engine... libpalermo: @(#)$CDS: libpalermo version 02/26/2004 03:08 (ncss17) $(sub-version 0226 ) Analog Kernel using -ANALOGCONTROL /nfs/ecsnas1/users/eegrad/bcheah/ibm13/sch.scs. Error found by spectre during circuit read-in. inv_ams: Parameter expression for `ngcon' is not supported. spectre terminated prematurely due to fatal error. ncsim: *E,RNAERR: Simulation is complete, analog initialization error. ---------------------------------------------------- Please help. Thank you very much. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Andrew Beckett on Jul 18th, 2005, 7:19am My guess would be that in the CDF for the transistors, where the ngcon parameter is defined, it does not have parseAsNumber set to "yes". As a result, the AMS netlister (quite rightly) netlists it as a string, and then this leads to the compilation error. I can only assume the different accounts are accessing different versions of the library containing the transistor definitions? Regards, Andrew. |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 18th, 2005, 8:26am Andrew, Thanks for the reply. That explains a lot. Both my accounts are accessing the same version of ibm 0.13 um technology but in a different path. I have 2 copies of the identical library installed on separate servers. Where would look for to enable the parseAsNumber to "yes" for the ngcon parameter? Where would you suggest to look for the CDF parameter settings? or I'm not suppose to change it. Thank you very much for your help. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Andrew Beckett on Jul 18th, 2005, 9:49pm In the CIW, use Tools->CDF->Edit CDF. Then fill in the library name and cell name of the transistor component. If you were to change this, you'd need to set the CDF Type to "Base" (rather than the default, which is "Effective"). Then go to the parameters section. Hit the Edit button at the top of the parameters section, and then in the form that pops up, there's a cyclic field which shows the parameter name. Change that to ngcon, and you should see the settings for the ngcon parameter. I would expect to see this as being as a string type. The key thing though is that parseAsNumber needs to be set to "yes". If that's not it, perhaps you can list here what the settings on the form for ngcon are for the two different accounts? Regards, Andrew. |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 19th, 2005, 7:52am Hi Andrew, Thanks for the valuable knowledge. I solved my problems already. Thank you very much. I do have another question. From my previous posting, I mentioned that my first problem was I was using global vdd and vss in my schematics and the generated netlist cannot be parsed into the simulator. I solved it by changing the global sources (vdd! & vss!) to vdd and vss. Is there any way around this because if there's an easier way for AMS to recognize global sources (which I think it should) rather having me changing each and every schematic in my design with vdd and vss. I'm thinking it must be my settings again. It would be very helpful if you could help me out on this too. Thank you very much. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Andrew Beckett on Jul 19th, 2005, 10:56am I'm afraid your description of this new problem doesn't make much sense to me. I've not seen any problems with having global nodes called gnd! and vdd! (etc) in a schematic, resulting in a netlist for AMS which doesn't compile. Some details might clarify what your problem is? Regards, Andrew. |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 20th, 2005, 6:31am Hi Andrew, I'm sorry for not being clear with my question. I'm using inout pins as my vdd! and vss! in my schematics. When I simulate them with just spectre, they are fine. But when I uses AMS environment. I was getting the following errors: --------------------------------------------------- ncelab: *E,CUCFUN: instance 'ams_alias_inst_0' of the unit 'cds_alias' is unresolved in 'thesis.reg15:schematic'. ncelab: *E,CUCFUN: instance 'ams_alias_inst_1' of the unit 'cds_alias' is unresolved in 'thesis.reg15:schematic'. ncelab: *E,CUCFUN: instance 'ams_alias_inst_0' of the unit 'cds_alias' is unresolved in 'thesis.dff:schematic'. ... I noticed that my generated netlist have some of the 'cds_alias' generated as shown below: ---------------------------------------------------- // Verilog-AMS netlist generated by the AMS netlister, version 5.0.32.500.10. // Cadence Design Systems, Inc. `include "disciplines.vams" module halfAdder2 ( A,S,Cout,\vss! ,\vdd! ,B ); input A; output S; output Cout; inout \vss! ; inout \vdd! ; input B; cds_alias #(.width(1)) (* integer library_binding = "basic"; integer view_binding = "functional"; *) ams_alias_inst_0 (\vss! , cds_globals.\vss! ); cds_alias #(.width(1)) (* integer library_binding = "basic"; integer view_binding = "functional"; *) ams_alias_inst_1 (\vdd! , cds_globals.\vdd! ); \or (* integer library_binding = "thesis"; *) I3 ( .A( A ), .F( net10 ), .B( B ) ); inv (* integer library_binding = "thesis"; *) I2 ( .Vout( net9 ), .Vin( Cout ) ); ... --------------------------------------------------- As I mentioned in the previous post, I solved it by naming my global vdd! and vss! as just vdd and vss for each design. But it's too much of a hassle to do that if I need to do it for all my schematics. Plus, I have re-wire most of my design in that case. Yesterday, I found another way to get rid of the problem. I used the symbol of vdd and vss from "analogLib" library instead of creating my own pins. AMS generated the netlist without the "cds_alias" lines. It seems to solve the problem. If you know of any other ways, please let me know. If any of these make sense to you, could you explain to me why this is happening? Thank you very much. If you need any more information, I would gladly provide. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 20th, 2005, 7:49am Andrew or anyone out there, I had fixed all the previous errors. I am able to netlist my whole design already. But now I'm facing another error. I cannot elaborate my design due to some internal error shown as follow: ======================================================================== Elaborating thesis.ideal_adc_13bits_test2:config - ncelab thesis.ideal_adc_13bits_test2:config -snapshot ideal_adc_13bits_test2:ams1121348439832 -cdslib /nfs/ecsnas1/users/eegrad/bcheah/ibm13/cds.lib -hdlvar /nfs/ecsnas1/users/eegrad/bcheah/ibm13/hdl.var thesis.cds_globals:ideal_adc_13bits_test2_config -errormax 500 -discipline logic -timescale 1ns/1ns -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -neverwarn -update -omicheckinglevel Standard -access +r-w-c ncelab: 04.10-s025: (c) Copyright 1995-2004 Cadence Design Systems, Inc. ncelab: *internal* (rts_seghandler - SIGSEGV unexpected violation pc=0x7f9343d8 addr=0x0). Please contact Cadence Design Systems about this problem and provide enough information to help us reproduce it. ncelab: Memory Usage - 20.5M program + 7.4M data = 27.8M total ncelab: CPU Usage - 1.9s system + 1.0s user = 2.9s total (5.7s, 49.8% cpu) Error encountered during NC elaboration for configuration thesis.ideal_adc_13bits_test2:config. ======================================================================== Please help! Thank you very much in advance. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 20th, 2005, 12:10pm Hi Andrew or anyone, I had fix my previous segmentation fault problem already. I fixed it by using LDV 5.1 instead of LDV 4.1. It seems that LDV 4.1 has bugs. But I did ran into another problem. I need help to write connect rule files. I tried the one given in the affirmaAMS library but it didn't help. I'm attaching the errors that I got and the top module (ideal_adc_13bits_test2) generated netlist. Please help. I had been stuck with numerous problems for the past week already. Thank you very muchl. Boon-Siang ======================================================================== Elaborating thesis.ideal_adc_13bits_test2:config - ncelab thesis.ideal_adc_13bits_test2:config -snapshot ideal_adc_13bits_test2:ams1121348439832 -cdslib /nfs/ecsnas1/users/eegrad/bcheah/ibm13/cds.lib -hdlvar /nfs/ecsnas1/users/eegrad/bcheah/ibm13/hdl.var thesis.cds_globals:ideal_adc_13bits_test2_config my_connectrules E2L L2E -errormax 50 -discipline logic -timescale 1ns/1ps -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -neverwarn -update -omicheckinglevel Standard -access +r-w-c ncelab: 05.10-s021: (c) Copyright 1995-2005 Cadence Design Systems, Inc. net065 ), .bit5( net068 ), .bit12( net061 ), .bit2( net071 ), .bit11( | ncelab: *E,CUVNCM (../thesis/ideal_adc_13bits_test2/schematic/verilog.vams,38|39): No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical. net12 ) ); | ...... ncelab: *E,CUVNCM (../thesis/ideal_adc_13bits_test2/schematic/verilog.vams,44|4): No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical. ncelab: Memory Usage - 22.5M program + 112.8M data = 135.3M total ncelab: CPU Usage - 11.3s system + 61.0s user = 72.4s total (90.7s, 79.8% cpu) Error encountered during NC elaboration for configuration thesis.ideal_adc_13bits_test2:config. ======================================================================== ======================================================================== // Verilog-AMS netlist generated by the AMS netlister, version 5.0.32.500.10. // Cadence Design Systems, Inc. `include "disciplines.vams" module ideal_adc_13bits_test2 ( bit8,bit5,bit12,bit2,bit11,bit0,bit10, bit3,bit6,bit9,bit7,bit1,bit4 ); output bit8; output bit5; output bit12; output bit2; output bit11; output bit0; output bit10; output bit3; output bit6; output bit9; output bit7; output bit1; output bit4; FIR (* integer library_binding = "thesis"; *) I7 ( .in7( net066 ), .out4( bit2 ), .in0( net073 ), .out12( bit10 ), .in4( net069 ), .in1( net072 ), .out7( bit5 ), .out14( bit12 ), .out11( bit9 ), .out2( bit0 ), .out0( net058 ), .out8( bit6 ), .in10( net063 ), .out5( bit3 ), .out10( bit8 ), .in2( net071 ), .out6( bit4 ), .in9( net064 ), .in8( net065 ), .in5( net068 ), .in12( net061 ), .out3( bit1 ), .in6( net067 ), .in3( net070 ), .in11( net062 ), .out13( bit11 ), .Clk( net12 ), .out9( bit7 ), .out1( net057 ) ); ideal_adc_13bits (* integer library_binding = "thesis"; *) I6 ( .bit8( net065 ), .bit5( net068 ), .bit12( net061 ), .bit2( net071 ), .bit11( net062 ), .bit0( net073 ), .bit10( net063 ), .clk( net12 ), .bit3( net070 ), .bit6( net067 ), .analogSignal( net9 ), .bit9( net064 ), .bit7( net066 ), .bit1( net072 ), .bit4( net069 ) ); analogGen (* integer library_binding = "thesis"; *) I4 ( .Vdd( net11 ), .Vss( net10 ), .analsig( net9 ) ); clk_digital (* integer library_binding = "thesis"; *) I3 ( .clk( net12 ) ); endmodule ======================================================================== |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 20th, 2005, 1:55pm Hi all, I got another persisting error after I used ConnRules_full and I cannot even re-compile my design anymore in AMS Designer due to some file cache inconsistency problem. Does anyone know how to clear the cache? Here is the error: ======================================================================== Elaborating usrlib.adc_test:config - ncelab usrlib.adc_test:config -snapshot adc_test:ams1121892328071 -cdslib /nfs/ecsnas1/users/eegrad/bcheah/ibm13/cds.lib -hdlvar /nfs/ecsnas1/users/eegrad/bcheah/ibm13/hdl.var usrlib.cds_globals:adc_test_config ConnRules_full -errormax 50 -discipline logic -timescale 1ns/1ns -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -update -omicheckinglevel Standard -access +r-w-c ncelab: 05.10-s021: (c) Copyright 1995-2005 Cadence Design Systems, Inc. ncelab: *W,DLNCML: Multiple logical library mappings have been detected in the cds.lib. Directory used multiple times '/nfs/ecsnas1/users/eegrad/bcheah/ibm13/usrlib'. ncelab: *F,DLNFS: File system cache consistency check failed. Tool has made some changes to the library 'thesis' to recover from it. Pls compile your design again. If the problem still persists, then contact Cadence.. ncelab: Memory Usage - 22.5M program + 1.6M data = 24.1M total ncelab: CPU Usage - 0.1s system + 0.0s user = 0.1s total (1.4s, 8.1% cpu) Error encountered during NC elaboration for configuration usrlib.adc_test:config. ======================================================================== Please please help. Really struggling to get this to work. Thank you very much. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Andrew Beckett on Jul 20th, 2005, 10:51pm Quick suggestion, based on some limited research. It sounds as if the .pak file in the library thesis has got corrupted - I would try deleting the .pak file in that library, and recompiling. Also, fix the multiple references to the same directory in your cds.lib file - perhaps that might be related? If you can access sourcelink, solution 11177990 looks relevant. Andrew. |
Title: Re: Error Message in NCSIM Post by Boon-Siang on Jul 21st, 2005, 7:00am Thanks, Adrew. After I removed those files, it fix everything. But I still have to the problem of running my design(FIR filter) with my ideal ADC. It still gave segmented fault with the LDV 5.1. My design is kinda big. It takes AMS Designer 10 minutes to finish compiling it and when I try to simulate it, it takes about 45 minutes before it tells me it has segmented fault. Does the size of the design affects AMS Designer to get segmented fault? Something to do with memory? I was thinking of make a smallerversion of my design to test it. Anyone has an idea? Thank you. Boon-Siang |
Title: Re: Error Message in NCSIM Post by Andrew Beckett on Jul 31st, 2005, 9:42pm I have no idea what is causing the segmentation fault - it could be almost anything. I would however suggest trying a more recent version than LDV51 - since LDV51 there has been IUS53, IUS54 and IUS55, so you are a few releases back... Regards, Andrew. |
Title: Re: Error Message in NCSIM,registers cannot drive Post by Siva on Nov 14th, 2005, 5:33pm Hi all, I was getting the error Registers cannot directly connect to analog ports. So used assign c=control; then it is giving "ncelab:*E,CUVNCM : No connection module found need inoutports of continuous discipline electrical,discrete discipline logic. I am using Cadence LDV 5.1 NCSimulator. Could anybody tell me what the problem is and how to resolve? I really appreciate your help. Thanks in advance. Siva verilog-ams CODE for switch : `timescale 10ps / 1ps `include "disciplines.vams" module testbench (); electrical gnd; ground gnd; reg control; logic c; initial control=0; always #100 control=~control; assign c = control; switch sw0 (p, gnd, c); vsource #(.type("sine"), .ampl(1.0), .dc(5), .freq(100M)) v0 (vp, gnd); resistor #(.r(10k)) r0 (vp, p); endmodule `timescale 1ns / 1ps `include "disciplines.vams" module switch (p, n, s); parameter real ron = 10.0 from (0:inf); // on resistance (ohms) parameter real roff = 100.0M from (ron:inf);// off resistance (ohms) parameter real td = 0.0; // delay time (s) parameter real tr = 20n; // rise time (on -> off) (s) parameter real tf = 20n; // fall time (off -> on) (s) input s; logic s; electrical p, n; real reff; analog begin @(posedge s) reff = ron; @(negedge s) reff = roff; @(initial_step) reff = (s ? ron : roff); I(p, n) <+ V(p, n) / transition(reff, td, tr, tf); end endmodule |
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