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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Current sense https://designers-guide.org/forum/YaBB.pl?num=1121766972 Message started by noreng on Jul 19th, 2005, 2:56am |
Title: Current sense Post by noreng on Jul 19th, 2005, 2:56am How do I make a current sense in Verilog-A? |
Title: Re: Current sense Post by Eugene on Jul 19th, 2005, 9:00am If you simply want to sense a current so you can use it in the same module, simply use I(p,n). You may need to add a node for the current sensor. For example, suppose you want to sense the current flowing into an input pin, "in". Try: electrical inx; //defines an internal node ... LHS variable = ...I(in,inx)...;//uses sensed current You would then use inx inside your module in place of in. Beware that the current sensor shorts the nodes "in" and "inx" together. The current sensor is like a voltage source that has zero volts across it. |
Title: Re: Current sense Post by Geoffrey_Coram on Jul 19th, 2005, 9:12am Eugene - I think the recommended way to sense a port (terminal) current is with LHS = ... I(<in>) ... ; -Geoffrey |
Title: Re: Current sense Post by Eugene on Jul 19th, 2005, 10:27pm Thanks Geoffrey. Am I correct in assuming the single node current sensor only works for ports? |
Title: Re: Current sense Post by noreng on Jul 20th, 2005, 12:19am Thanks for your reply. Yes, I want to sense a port current and I've noticed that I(in) short circuits in to ground. However, I've tried your advice, but it didn't work. I get the following error messages: In file src/switch_sense.vla line 52: LHS sense=I(p); ^ [Failure] Syntax error : received IDENTIFIER while expecting '(' or '[' or '=' and In file src/switch_sense.vla line 52: LHS=I(p); ^ [Error] Symbol LHS has not been defined Error: (valog) Compilation: Analysis failed. |
Title: Re: Current sense Post by Andrew Beckett on Jul 20th, 2005, 3:53am It wasn't something to use literally. LHS meant "Left Hand Side" and was a placeholder for some left-hand-side expression (e.g. some variable, or a contribution statement, or something like that). Try reading Ken and Olaf's book on Verilog-AMS. Andrew. |
Title: Re: Current sense Post by Geoffrey_Coram on Jul 20th, 2005, 4:21am Eugene - Yes, that is special syntax only for ports (aka terminals). One typical use of a current sensor is a controlled source: Code:
As noted before, this shorts "in" to ground, and then measures the current flowing through this shorted branch to generate the output voltage. One might use the I(<port>) syntax in a more complicated module Code:
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