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https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> One more question about PFD/CP phase noise https://designers-guide.org/forum/YaBB.pl?num=1121990416 Message started by boa on Jul 21st, 2005, 5:00pm |
Title: One more question about PFD/CP phase noise Post by boa on Jul 21st, 2005, 5:00pm I have already asked this question in the thread about the noise in PFD/CP but, as there were no responses, I dare to ask it again here :) I have extracted the output noise of PLL blocks using PNoise analyses as described in Ken's paper and built a linear phase-domain PLL model. The simulated results are pretty close to the measurements from the chip and the phase-domain model shows that the low-offset in-band phase noise of PLL is donimated by PFD/CP block. The CP is a simple single-ended charge pump with switch in source. I looked at the PFD/CP output noise contributors and the major noise was due to flicker noise of NMOS cascode bias transistors in CP which is logical. But after I increased the length of the bias transistors, the next major noise contibutors were transistors in the inverters which serve as buffers for the UP & DOWN signal between PFD and CP. The buffer is a chain of 2 inverters, so Cadence shows that noise comes from the NMOS in the second inverter. If I further on increase both W&L in the second inverter, then the major noise contributors are transistors in the 1st inverter. What can be an explanation for that? Does it mean that, according to simulation, the main output noise is at the moment of switching UP & DOWN signals (when these signals are near inverters tresholds)? Is such noise model of PFD/CP in PLL realistic? ??? A few words about simulation setup: The delay between Fv & Fr is zero (I want to get the noise at the lock state). The PFD clock freq is 600 kHz, in PSS number of output harmonics is 30, in PNoise maxsideband=30, I am looking at noise at 1-10kHz. |
Title: Re: One more question about PFD/CP phase noise Post by rf-design on Aug 31st, 2005, 6:06am I think you refer to the following post http://www.designers-guide.org/Forum/?board=jitter;action=display;num=1037357676;start=0#0 The concideration is right. The phase noise at the LO level is filtered by the transfer function of noise sources within the PLL loop to the LO. It is more or less a bandpass function with center at the PLL bandwidth. Higher frequency components are filtered by the analog loop filter. Lower frequency components are rejected by the loop gain. What is interesting is that I could differentiate 2 noise sources. The first is the current noise while the charge pump is on. The second is the timing jitter of switching on/off. I thought that both could not be simulated within the same analysis type. Regarding your circuit tuning you have to trade the speed of switching, which reduces timing jitter and a possible higher 1/f contribution. Please also add the linear current noise and weight the noise related to the ratio on-time/period. |
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