The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> discipline error in Verilog-AMS
https://designers-guide.org/forum/YaBB.pl?num=1122003354

Message started by coldfire1029 on Jul 21^st, 2005, 8:35pm

Title: discipline error in Verilog-AMS
Post by coldfire1029 on Jul 21^st, 2005, 8:35pm

I am trying to simulate the D-flop that is in this website.

http://www.designers-guide.org/VerilogAMS/functional-blocks/dff/dff.va

I am getting error msg: . Help appreciated...thx.

ncelab: *E,CUVDNF (/test/dflop_tb/schematic/verilog.vams,17|15): Could not determine discipline for this expression .
qb ), .q( q ), .d( d ) );
|

Here is my testbench:
`include "disciplines.vams"

module dflop_tb ( qb,q,d );

output qb;
output q;
input d;

dff1 (*
integer library_binding = "test";
*)
I2 ( .clk( net13 ), .qb(
qb ), .q( q ), .d( d ) );

vsource #(.delay(5u), .type("pulse"), .period(500p), .width(250p), .edgetype("linear"),
.val0(0.0), .dc(0), .rise(50p), .val1(1), .fall(50p)) (*
integer
library_binding = "analogLib";
*)

Title: Re: discipline error in Verilog-AMS
Post by Geoffrey_Coram on Jul 22^nd, 2005, 12:41pm

The dff1 that's on the web site sets its ports to be "voltage"

output q; voltage q; // Q output

I'm used to seeing ports declared as "electrical." In this case, it shouldn't matter, since the through variable (current) isn't used. However, it may be that the simulator you have doesn't actually define "voltage" as a discipline, but rather only defines the nature "Voltage." Try changing them to "electrical", or add this after the `include:

discipline voltage
potential Voltage;
enddiscipline

-Geoffrey