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Design Languages >> Verilog-AMS >> wreal in digital context
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Message started by Monia on Jul 22^nd, 2005, 9:05am

Title: wreal in digital context
Post by Monia on Jul 22^nd, 2005, 9:05am

I have the following code:

.......
real sample, OutInt;
wire dsample;

always @(posedge dsample) begin
OutInt = sample;
<other digital setting>
end
.......

where "sample" is controlled in another process and
it has a behavior like a step.
Instead OutInt is changing even if dsample is stable
and it behaves like a ramp.

Can you explain me why?

I'm expecting OutInt stays constants and it changes
only @ posedge of dsample.

Title: Re: wreal in digital context
Post by jbdavid on Aug 3^rd, 2006, 6:18am

Are you SURE the value is changing between, or is your Waveform viewer "connecting the dots" between the values..
This is the simvision default setting for real and wreal signals.