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Modeling >> Semiconductor Devices >> about the physics of SOI
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Message started by jason_class on Aug 14^th, 2005, 5:55am

Title: about the physics of SOI
Post by jason_class on Aug 14^th, 2005, 5:55am

Hello All

Anyone has any good document or good link to share details on SOI cmos devices in how does it work, why it has better advantages using physics and electronic equation?
Kindly share with me.
Thank you

best regards
Jason

Title: Re: about the physics of SOI
Post by vivkr on Aug 18^th, 2005, 2:23am

Hi Jason,

Just one paper to suggest but it has further links to more SOI stuff in the referencs.

Try "A gm/Id based methodology for ....." by Silveira et. al. in JSSC Sep. 1996.

The authors present a very brief but useful discussion about the merits of SOI for analog design such as higher intrinsic gain owing to no depletion capacitance below the gate and of course, no body terminal or body effect.

Additionally, SOI is supposed to have advantages with respect to reliability and radiation hardness. But you will probably find more on that elsewhere.

Vivek

Title: Re: about the physics of SOI
Post by jason_class on Aug 18^th, 2005, 7:34am

Hi Vivek

Thanks for the reference. Is it under IEEE paper collection?

I read from book that the background doping for Nwell for a fully depleted soi device is lower than that of partially depleted soi. May I know what is the reason?
Then which semiconductor physics equation we can use to explain this effect of difference in doping?

Kindly enlighten

Thank you all

best regards
Jason

Title: Re: about the physics of SOI
Post by vivkr on Aug 18^th, 2005, 10:30pm

Hi Jason,

I myself am not very familiar with SOI. But I know that IBM was one of the
first proponents of this technology along with AMD. As this is a relatively new feature, most of the standard textbooks on semiconductor devices dont have any information on this. However, you will probably find enough journals and artciles or even links to books on the web. One article I found was:

http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3402&pg=1

As for partially depleted and fully depleted devices, I would say that the reason for doping the latter lightly would be to allow them to deplete more easily. The depletion region width is inversely proportional to the doping level. That would be a simple explanation for it.

And yes, I was referring to an IEEE JSSC article.

Hope that helps.

Vivek

Title: Re: about the physics of SOI
Post by jason_class on Aug 20^th, 2005, 1:19am

Hi Vivek

That's a cool answer
I will read out the paper.
You have been a great help here
Thanks Vivek

Jason