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Design Languages >> Verilog-AMS >> Current switching
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Message started by noreng on Aug 24^th, 2005, 3:40am

Title: Current switching
Post by noreng on Aug 24^th, 2005, 3:40am

I want to make a verilog-ams module which routes an incoming current through 2 voltage controlled resistors. The resistors are connected to a common node p and separate nodes n1 and n2.

Part of the code is shown below where reff1 and reff2 are the VCRs.

I(p,n1) <+ I()*reff1/(reff1+reff2);
I(p,n2) <+ I()*reff2/(reff1+reff2);

When running a simulation, the output currents approach zero amps. Seems like the simulator isn't able to have sort of the same current on both sides of the expressions.

Title: Re: Current switching
Post by Ken Kundert on Aug 24^th, 2005, 6:47am

Those are not resistors. They are current controlled current sources.

-Ken

Title: Re: Current switching
Post by noreng on Aug 24^th, 2005, 7:08am

reff1 and reff2 are defined as resistors, but have not been included since it is only the enclosed code which should be of interest.

Title: Re: Current switching
Post by Ken Kundert on Aug 24^th, 2005, 10:28am

With the code you have given, if I() is zero then both I(p,n1) and I(p,n2) will be zero. Is there any reason to believe that I() should not be zero?

-Ken

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 24^th, 2005, 10:37am

I always get myself confused when thinking about the "p" and "n" nodes of current sources ... maybe you've set something up so that zero is the only valid solution?

Since you're intending for the currents to add up to zero, let's build that assumption into the model:

I(n1) <+ I(p)*reff1/(reff1+reff2);
I(n2) <+ I(p)*reff2/(reff1+reff2);

Now, if there's a KCL problem because of the signs, you'll be dumping the excess into ground -- I(p) measures the short-circuit current on the branch from p to ground. Then you can multiply by -1 if the currents are all going in.

Title: Re: Current switching
Post by noreng on Aug 24^th, 2005, 11:21pm

The simulation result of zero is wrong.

In fact, I want to pass a dc current from spice into the verilog-a module and that the sum of the currents exiting from n1 and n2 should be equal to the current entering at p.

However, running a simulation gives a result near zero.

Title: Re: Current switching
Post by Ken Kundert on Aug 25^th, 2005, 12:05am

You have given us so little information it is very difficult to help you. Perhaps you give us the whole model definition, or at least more of it.

So far, if we just focus on node p, what we have is that
I(p) + I(p) = I(p)*(reff1+reff2)/(reff1+reff2)
which simplifies down to
2 = 1
This suggests that the model is ill-formed. Is there another path for the current entering p?

-Ken

Title: Re: Current switching
Post by noreng on Aug 25^th, 2005, 12:26am

The spice code follows below.

vdda avdd 0 vdd
iref avdd top iref

ys1 test_switch port: top out1 out2 0

rl1 out1 0 rload
rl2 out2 0 rload

Thus, current from the iref source should enter at top which is the same node as p in the verilog-a module.

The current should exit at out1 and out2 (corresponding to n1 and n2 in the verilog-a module).

Thus, Itop = Iout1 + Iout2

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 25^th, 2005, 5:29am

Ken Kundert wrote on Aug 25^th, 2005, 12:05am:

So far, if we just focus on node p, what we have is that
I(p) + I(p) = I(p)*(reff1+reff2)/(reff1+reff2)
which simplifies down to
2 = 1

Ken -
I thought that I(p,n1) <+ contributes current to the (unnamed) branch from p to n1 -- similar for I(p,n2). I() measures the port current -- I visualize it as a 0V voltage source between the terminal p and an internal node, from which the two current-source branches feed out. So, I don't see the 2=1 problem you claim.

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 25^th, 2005, 5:49am

This is "test_switch.va"

Code:

`include "discipline.h"

module test_switch(p,n1,n2);
inout p,n1,n2;
electrical p,n1,n2;
parameter real reff1 = 1 from (0:inf);
parameter real reff2 = 1 from (0:inf);

analog begin
I(n1) <+ -I(p) * reff1/(reff1+reff2);
I(n2) <+ -I(p) * reff2/(reff1+reff2);
end
endmodule

and here is my netlist:

Code:

*
simulator lang=spectre

vdda (avdd 0) vsource dc=5
iref (avdd top) isource dc=1

ahdl_include "test_switch.va"
ys1 (top out1 out2) test_switch reff1=1 reff2=2

rl1 (out1 0) resistor r=1k
rl2 (out2 0) resistor r=1k

save ys1:all rl1:all rl2:currents top out1 out2
dc1 dc dev=iref start=0 stop=5

I see the current divided in a 1:2 ratio.

I don't quite understand why I get a different answer if I use
I(p,n1) <+ I() * reff1/(reff1+reff2);
I(p,n2) <+ I() * reff2/(reff1+reff2);
I get a 1:2 ratio, and the currents aren't all zero, but the currents into test_switch ys1 don't add up to zero.

Title: Re: Current switching
Post by noreng on Aug 25^th, 2005, 6:24am

I've been experimenting some more with the current switching.

If I let the resistors stay constant in a transient analysis, the output currents are as expected. However, if I let the resistors vary vs. time, i.e. I use voltage controlled resistors controlled by a square wave and its inverse, the output currents become zero.

If I instead calculate the output currents, set them equal to a real variable and write the values to a file, the values in the file look normal.

Title: Re: Current switching
Post by Ken Kundert on Aug 25^th, 2005, 8:09am

Okay, sorry. The 2 = 1 statement was a mistake, but the model as originally given is still ill-conditioned. To see it, call (p,n1) branch 1 and (p,n2) branch 2. Clearly,
I() = I(branch1) + I(branch2)
Now
I(branch1) = a1*I()
I(branch2) = a2*I()
where a1=reff1/(reff1+reff2) and a2 = reff2/(reff1+reff2). Thus,
I() = (a1+a2)*I()
which is only true if (a1+a2) is exactly equal to 1. If it is not, there is no solution. Thus, this system is singular, which would explain the odd behavior.

You would be better served reformulating the model as Geoffrey proposed. By doing so, you eliminate the ill-conditioning and cleary define the input impedance of your model to be 0 and your output conductance of both outputs to be 0.

Oh, and reff1 and reff2 are not resistors. They are numbers that determine the current division ratio between two current controlled current sources. Nowhere does the model exhibit a resistance of either reff1 or reff2.

-Ken

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 25^th, 2005, 8:28am

Noreng -
I'm not sure what you mean when you say "resistors" -- as Ken pointed out, reff1 and reff2 are just numbers. I don't think you're varying the load resistors rl1 and rl2.

Perhaps you are doing something odd to generate the values of reff1 and reff2 from your square wave? In which case, you should show us how those values vary.

Ken -
Since (a1+a2) = (reff1+reff2)/(reff1+reff2), won't this always be exactly 1? Are you concerned about roundoff?

Title: Re: Current switching
Post by Ken Kundert on Aug 25^th, 2005, 11:18am

Yes.

-Ken

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 25^th, 2005, 11:28am

Actually, the problem is this: noreng has defined a current-source cut-set, which is a topology error. The node "top" can be isolated by removing a cut-set of only (ideal) current sources, which means that its voltage is arbitrary.

Probably what's happening is noreng's simulator is adding a Gmin from top to ground, and *all* the current from the iref current source is going through this conductance. The fact that v(top) is now going through the roof doesn't matter; the current sources don't care.

My recommended solution fixes this by shorting "top" to ground, so that its voltage is known.

Title: Re: Current switching
Post by Ken Kundert on Aug 25^th, 2005, 5:51pm

I believe the problem is more severe than that. It hard to know because we still have not yet seen the full model, but I believe that the problem is in the model itself. Even if one provided a resistor to ground from terminal p the system would still be ill-conditioned. The reason being that the model consists a current probe in series with a (pair of) current source, and the current source is forced to produce the exact same current that is measured by the probe. If this thing is driven by a resistive source, then the current is arbitrary. Any current will satisfy the circuit equations. If you force the current with a current source, then the voltage becomes arbitrary.

The model has to be rewritten so that the current through the sources is not taken from the probe.

-Ken

Title: Re: Current switching
Post by noreng on Aug 26^th, 2005, 1:22am

Seems like I have been too sloppy formulating the problem,

There is a 10Meg resistor in parallel with the current source.

reff1 and reff2 are as you said numbers and not resistances. Their values are calculated by a piecewise linear model controlled by the input voltage. Thus, when the control voltage is below a certain threshold, reff is max. When the lower threshold is exceeded, reff decreases linearly with the control voltage. Finally, when the high threshold is crossed, reff will reach its minimum value.

Besides, the output currents are calculated as follows:

I(p,n1) = I()*(reff1+rload)/(reff1+reff2+2*rload)
I(p,n2) = I()*(reff2+rload)/(reff1+reff2+2*rload)

I'm wondering if it is the piecewise linear function which causes problems. Maybe it can be replaced by an inverse tangent function.

Title: Re: Current switching
Post by noreng on Aug 26^th, 2005, 3:24am

Now, I have removed the piecewise linear values and replaced them by linear ones. That is, reff1 is always decreasing with increasing vctr1 and vice versa.

I'm able to switch currents as wanted. However, the p node of the verilog-a module is being pulled up to VDD when I'm simulating. Although this works fine for an ideal current source, it won't work with a transistor current source.

Any suggestions? Thanks in advance.

module test_switch (p,n1,n2,s1,s2,z); // p/n1,n2: i/o; s1,s2: ctrl; z: avss
parameter real ron = 10 from (0:inf); // on resistance (ohms)
parameter real roff = 100M from (ron:inf); // off resistance (ohms)
parameter real rload = 1k from (0.1:inf); // load resistance

inout p, n1, n2, z, s1, s2;
electrical p, n1, n2, z, s1, s2;

real reff1, reff2, vctr1, vctr2;

branch (p,n1) res1;
branch (p,n2) res2;

analog begin
vctr1 = V(s1);
vctr2 = V(s2);

reff1 = roff+(ron-roff)*vctr1;
reff2 = roff+(ron-roff)*vctr2;

V(p,n1) <+ I(p,n1)*reff1;
V(p,n2) <+ I(p,n2)*reff2;

I(res1) <+ I()*(reff1+rload)/(reff1+reff2+2*rload);
I(res2) <+ I()*(reff2+rload)/(reff1+reff2+2*rload);
end
endmodule

Title: Re: Current switching
Post by noreng on Aug 26^th, 2005, 4:34am

Oops, one more error.

The voltage across the current source equals the supply voltage and not zero, making it possible to use the model together with a transistor current source.

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 26^th, 2005, 4:46am

noreng -
I still don't think you've understood the point of Ken's last post.

Even with the 10Meg resistor, your circuit is poorly formulated. The current can be divided arbitrarily between the 10Meg resistor and your vams module. The voltage on the "p" terminal of the module doesn't affect the current through it. You could have V(p) = 10Meg * iref + vdd and I()=0 (all the current flows back through the resistor), or you could have V(p)=vdd (no current through the resistor, hence it all flows through the "p" terminal) -- or anything in between!

Title: Re: Current switching
Post by noreng on Aug 26^th, 2005, 6:24am

You're right that I haven't understood Ken's last point.

Please explain the following:

The model has to be rewritten so that the current through the sources is not taken from the probe.

Thanks in advance.

Title: Re: Current switching
Post by Geoffrey_Coram on Aug 26^th, 2005, 7:36am

There's circular reasoning in your module.

Internally, the simulator knows that I() is the sum of all the currents of the branches terminating at "p"; but you've also set up equations such that the branch currents depend on I() -- and hence depend on themselves!!

Is there some reason you didn't like my approach,
I(n1) <+ I(p) * ...
I(n2) <+ I(p) * ...

The I(p) on the right-hand side creates a short from "p" to ground, thus making sure the module takes all the current available at the "p" terminal.

Title: Re: Current switching
Post by noreng on Aug 26^th, 2005, 7:56am

The only reason was a lack of understanding of Verilog-A.

Thanks for your help.