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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> Cadence ic subcikt netlisting w/0 a schematic view https://designers-guide.org/forum/YaBB.pl?num=1125462821 Message started by Carl Chao on Aug 30th, 2005, 9:33pm |
Title: Cadence ic subcikt netlisting w/0 a schematic view Post by Carl Chao on Aug 30th, 2005, 9:33pm Hi all, I'm using a Chartered 018um CMOS RF spice (hspice and spectre) library, in which all the MOS devices are defined as subcircuits. I 'm trying to create a cadence library for this spice library so that I can do interactive simulations with the Analog Environment in Cadence. But because of the large amount of parameters involved with these devices, I don't want to waste time to draw a schematic (with ideal devices) for each device and specify its parameters. Instead, I just want to create symbols of the devices and hopefully make a subcircuit call to their spice library after the Cadence netlisting procedure. I used to use Mentor's da_ic, and I know da_ic can perform netlist function if you provide only a symbol view and an (eldo)spice view. That's a very convinent feature, especially for RF design, because these days the rf spice model of the devices are so complicated that they must be modelled with lots of interconnected RCLs etc., and they can only be treated as a subcircuit instead of a primitive. I tried to play around to see if I can sort the above problem through, but so far not so good. Your help will be very appreciated! Hopefully Cadence also has the above mentioned feature, other wise I don't think Cadence will have too much attraction anymore, especially to the mixed signal design community now that Mentor also got its own version of RF simulator EldoRF ... CC |
Title: Re: Cadence ic subcikt netlisting w/0 a schematic Post by Geoffrey_Coram on Aug 31st, 2005, 6:00am Does the subckt take the same pins and parameters as the basic MOS device? (ie, you should have D G S B pins and L W parameters). In which case, you should be able to put in the standard MOS device from a standard library (analogLib?) and just give the model name that points to the subckt. It might be a little more difficult if you have a 5-terminal device (PMOS or NMOS in deep nwell) or if you need to vary the number of fingers (maybe you can write subckts for a couple fingers and call them rfnmos_16, rfnmos_32, etc. and have them call the master subckt). -Geoffrey |
Title: Re: Cadence ic subcikt netlisting w/0 a schematic Post by Carl Chao on Aug 31st, 2005, 8:45am Hi Geoff, Thanks very much for the reply. Yes, these devices have the same pin and parameters as a common MOS device. But if I use the standard MOS device from the standard library, the Cadence netlist would give me a device name started with M** instead of X** as for a subcircuit. (I'm not very familiar with Cadence, perhaps there's a way to change the prefix of the device name from like M** to X** automatically). Best regards, CC |
Title: Re: Cadence ic subcikt netlisting w/0 a schematic Post by msl on Aug 31st, 2005, 9:36am Hi Geoff, I have solved the problem after I checked one of the previous post by Andrew Beckett (thanks Andrew!!). The link is: http://www.designers-guide.org/Forum/?board=circuit;action=display;num=1118940189 Thanks! CC |
Title: Re: Cadence ic subcikt netlisting w/0 a schematic Post by John O Donovan on Aug 31st, 2005, 9:41am If you are using Spectre as the simulator then the element name prefix 'X' or 'M' does not matter. As long as the pins and parameters that you are passing are accepted by the subckt, it will work as is, i.e. M1 d g s b nmos w=1u l=1u nmos can be a model, subckt, Verilog-A module, primitive, etc. John |
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