The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Semiconductor Devices >> strained Si cmos
https://designers-guide.org/forum/YaBB.pl?num=1126841932

Message started by jason_class on Sep 15^th, 2005, 8:38pm

Title: strained Si cmos
Post by jason_class on Sep 15^th, 2005, 8:38pm

Hello All

I found that there are company that makes Strained Si substrate. But in IEEE papers I have, it never mentioned about Strained Si is made in the foundry during device processing or it is suppied by wafers vendor. Anyone knows about this?

Then from reading , I got the idea holes are present in compressive SiGe layer for pmos while electrons are present in the cap Strained Si layer. Is my understanding correct?
If yes, this means holes are always confined in the buried compressive SiGe layer.
Kindly enlighthen

Thank you

best regards
Jason