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Design Languages >> Verilog-AMS >> Error in simulating a VCO in veriloga
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Message started by moisiad on Sep 29^th, 2005, 8:02am

Title: Error in simulating a VCO in veriloga
Post by moisiad on Sep 29^th, 2005, 8:02am

Hi

I am using Spectre in Cadence. I am trying to perform a PSS and Pnoise analysis of a veriloga behavioral model (given below) of a VCO with FM jitter . However i am getting the following error message:

"Distributed components and components with hidden state are not allowed with this analysis", which most probably refers to the line where dT is declared.

How can i overcome this problem

Thanks

// Voltage Controlled Oscillator with Jitter
‘include “discipline.h”
‘include “constants.h”
module vco (out, in);
input in; output out; electrical out, in;
parameter real Vmin=0;
parameter real Vmax=Vmin+1 from (Vmin:inf);
parameter real Fmin=1 from (0:inf);
parameter real Fmax=2*Fmin from (Fmin:inf);
parameter real Vlo=–1, Vhi=1;
parameter real tt=0.01/Fmax from (0:inf);
parameter real jitter=0 from [0:0.25/Fmax);
parameter real ttol=1u/Fmax from (0:1/Fmax);
real freq, phase, dT;
integer n, seed;
analog begin
@(initial_step) seed = –561;
// compute the freq from the input voltage
freq = (V(in) – Vmin)*(Fmax – Fmin)
/ (Vmax – Vmin) + Fmin;
// bound the frequency (this is optional)
if (freq > Fmax) freq = Fmax;
if (freq < Fmin) freq = Fmin;
// add the phase noise
freq = freq/(1 + dT*freq);
// phase is the integral of the freq modulo 2p
phase = 2*‘M_PI*idtmod(freq, 0.0, 1.0, –0.5);
// update jitter twice per period
// 1.414=sqrt(K), K=2 jitter updates/period
@(cross(phase + ‘M_PI/2, +1, ttol) or
cross(phase – ‘M_PI/2, +1, ttol)) begin
dT = 1.414*jitter*$dist_normal(seed,0, 1);
n = (phase >= –‘M_PI/2) && (phase < ‘M_PI/2);
end
endmodule

Title: Re: Error in simulating a VCO in veriloga
Post by Andrew Beckett on Sep 29^th, 2005, 10:22am

I don't think you'll get it to converge using this kind of approach, because even if the hidden state variables were handled somehow, the model will not reach a steady state because of the variation in the period from cycle to cycle in the time domain.

If you modelled the jitter using noise sources (see the "osc" model in rfLib - it's written in spectreHDL, but you'll get the idea), then the phase noise is only added during the pnoise analysis - and so would not affect the steady state.

Regards,

Andrew.

Title: Re: Error in simulating a VCO in veriloga
Post by Ken Kundert on Sep 29^th, 2005, 8:37pm

The seed variable represents hidden state (its value is saved from one timestep to the next). You might be able to add the (* ignore_state *) attribute on seed, but you would still have the problem's Andrew pointed out.

-Ken