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Design >> Mixed-Signal Design >> interface MSHDL-(low level analog)?
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Message started by Denis on Oct 5^th, 2005, 5:35am

Title: interface MSHDL-(low level analog)?
Post by Denis on Oct 5^th, 2005, 5:35am

Help me!
Get me answer for sensitive issue. How can I connect VHDL-AMS/Verilog-AMS electrical/logical terminal to low level (transistor) analog circuitry for Cadence AMS Designer Environment. Please, give me advice for all cases.

Title: Re: interface MSHDL-(low level analog)?
Post by Andrew Beckett on Oct 5^th, 2005, 7:23am

Please try reading the manual rather than asking a ridiculously open ended question like this. That's what the documentation is for...

Regards,

Andrew.

Title: Re: interface MSHDL-(low level analog)?
Post by jbdavid on Oct 5^th, 2005, 4:55pm

We'll I had a gentler reply going but the page reset itself while I was writing it..
Please go look at www.bmas-conf.org
and see my Verilog-AMS tutorial from 2002, or my more recent paper from 2004.. BTW MY stuff isn't the ONLY good stuff there..
Of course even BETTER would be to buy a copy of Ken's book from this site and get reading..

The Quick answer is "structural" modeling which can be combined with behavioral modeling..
and some of that I answered in a couple of posts last week.. (Note.. This is PROPERLY a topic for the Verilog-AMS language section!)
jonathan

Title: Re: interface MSHDL-(low level analog)?
Post by Denis on Oct 5^th, 2005, 11:34pm

Sorry for ridiculously question. I read documentation for Cadence AMS Designer, but I did not find answers for all my questions.
I understood that terminals:
VHDL/Verilog | VHDL/Verilog - connect directly
VHDL/Verilog | spice analog - connect via IE
VHDL-AMS | spice analog - impossible
futher
Verilog-AMS | spice analog - connect directly? \
VHDL-AMS | Verilog-AMS - impossible - It is question???
VHDL/Verilog | Verilog-AMS - connect via IE? /
* Here VHDL/Verilog - logic ports, Verilog-AMS/VHDL-AMS - electrical terminals.

Title: Re: interface MSHDL-(low level analog)?
Post by Andrew Beckett on Oct 9^th, 2005, 11:18pm

Let me describe it another way, which might make things clearer. Verilog-AMS supports the idea of automatic connectmodule (a.k.a. interface elements) insertion at discipline boundaries. VHDL-AMS does not (it's a strongly typed language, and as a result, the "disciplines" of connected ports must match).

What that means is that we are free to insert connectmodules within Verilog-AMS code, but cannot do so in VHDL-AMS.

That said, the electrical disciplines in VHDL-AMS and Verilog-AMS match, and so these can be connected directly. Similarly the standard logic disciplines between the two languages match. Also, by adding a layer of Verilog around some VHDL/VHDL-AMS code (sometimes known as a "shell" or "wrapper"), you then have somewhere for the automatic connectmodule insertion to work.

This is a slightly simplistic view of things, but hopefully should be clear enough to answer your questions by explaining how it works rather than answering the specific question and giving you no understanding of why.

Regards,

Andrew.

Title: Re: interface MSHDL-(low level analog)?
Post by DenisMark on Oct 12^th, 2005, 7:17am

Thank you very much, Andrew. :D

Title: Re: interface MSHDL-(low level analog)?
Post by DenisMark on Oct 13^th, 2005, 8:01am

Please, one more question. When I connect two VHDL_AMS terminals with electrical disciplines (branch) to spectre resitor I have mistake on elaboration stage. Why. Does electrical discipline of VHDL-AMS is fully supported by Cadence AMS Designer?

Title: Re: interface MSHDL-(low level analog)?
Post by Andrew Beckett on Oct 14^th, 2005, 2:58pm

Without knowing how the connection has been done, it's virtually impossible to answer this question. Did you connect it using a Verilog-AMS netlist, a schematic netlisted as Verilog-AMS, or a referenced spectre netlist. The last one of these probably wouldn't work, because I don't think VHDL-AMS supports connecting to built-in primitive devices or (say) spectre netlists...

A precise description would help answer this properly.

Andrew.

Title: Re: interface MSHDL-(low level analog)?
Post by DenisMark on Oct 17^th, 2005, 3:46am

In detail:
// Verilog-AMS netlist generated by the AMS netlister, version 5.0.33_USR1.35.4.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
`include "constants.vams"

module test ( );

resistor #(.r(1K)) (* integer library_binding = "analogLib"; *) R0
( cds_globals.\gnd! , net1 );

generator (* integer library_binding = "testlib"; *) I0 ( .aout( net1 ),
.ref( cds_globals.\gnd! ) );

endmodule

This is test VHDL-AMS generator description:
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

entity generator is
generic (
ULO : real := 0.2; -- output voltage for logic '0'
UX : real := 2.5; -- output voltage for logic unknown or high-impedance
UHI : real := 4.8; -- output voltage for logic '1'
RON : real := 0.1; -- internal resistance for strong states
RWK : real := 1.0e4; -- internal resistance for weak states
ROF : real := 1.0e9; -- internal resistance for high-impedance state
TT : real := 1.0e-9); -- output transition time
port (
terminal aout, ref: electrical); -- analog outputs
end generator;

architecture bhv of generator is
type real_table is array (std_logic) of real;
constant R_table: real_table := (RON, RON, RON, RON, ROF, RWK, RWK, RWK, ROF);
constant V_table: real_table := (UX, UX, ULO, UHI, UX, UX, ULO, UHI, UX);
quantity uout across iout through aout to ref;
signal reff: real := 0.0; -- effective resistance
signal veff: real := 0.0; -- effective voltage
signal din: std_logic := '0'; -- logic input
begin
din <= not din after 10us;
reff <= R_table(din);
veff <= V_table(din);
uout == veff'ramp(TT) + iout*reff'ramp(TT); -- iout is defined from aout to ref
end architecture bhv;

Thanks...

Title: Re: interface MSHDL-(low level analog)?
Post by Andrew Beckett on Oct 19^th, 2005, 2:30am

I tried this with both LDV51 and IUS55 - and it compiled, elaborated, and simulated in both cases. So what version of the simulator are you using (which is more imporant if you're getting elaboration errors than the IC version).

For the record, I did the following. First I created generator.vhd, and test.vams with the code you gave. I created a cds_globals.vams with the following:

Code:

`include "disciplines.vams"

module cds_globals;

electrical \gnd! ;
ground \gnd! ;

endmodule

I created a cds.lib file as follows:

Code:

INCLUDE $LDVHOME/tools/inca/files/IEEE_vhdlams/cds.lib
define worklib worklib

and an hdl.var file as follows:

Code:

INCLUDE $LDVHOME/tools/inca/files/hdl.var
DEFINE work worklib

I created a directory called "worklib". Then I created a simple analog control file:

Code:

//
tran tran stop=100n

Finally I compiled, elaborated, and simulated:

Code:

ncvhdl -ams generator.vhd
ncvlog -ams test.vams cds_globals.vams
ncelab test cds_globals
ncsim -analogcontrol control.scs test

Apart from a minor warning when compiling the VHDL-AMS code, everything was fine...

Regards,

Andrew.