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Design >> Mixed-Signal Design >> Problem in cascading sample&hold stages
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Message started by moisiad on Oct 10^th, 2005, 7:00am

Title: Problem in cascading sample&hold stages
Post by moisiad on Oct 10^th, 2005, 7:00am

Hi all

I have designed the sample&hold stage of a 8bit pipeline ADC with specs VDD=1V, F=30MHz. The stage incorporates a folded cascode OPAMP (PM=60, gain 70db, settling time=14ns) and the sample and hold circuit is from Baker - CMOS Mixed Signal Circuit design, pp.355.

The stage operates good enough when it is driving just a capacitive load. I have managed to get the triangle Vin-Vout characteristic which is very good.

However when i place as a load the same SH stage the output is distorted exhibiting large spikes and in some cases no correct values. I suppose that is due charges that passes from one stage to another, as there is no any buffer between the stages.

Have every of you noticed such a problem? Is it common in SC circuits and how can be fixed such a problem?

Thanks

Title: Re: Problem in cascading sample&hold stages
Post by Paul on Oct 13^th, 2005, 1:46pm

Hi,

right now I don't have access to Baker's book, but I have the following hypothesis. In the first case, your increment from sample to sample is relatively small (as you are doing a tri-wave sweep), so the charge the S&H has to deliver during each cycle is small. In the second case, the charges on the input capacitor of the second stage are transfered to the hold capacitor once a period, i.e. the capacitor is discharged when it is connected back to the output of the first stage. If this is the case (please confirm), then the amount of the charge the S&H has to deliver each clock cycle is much smaller and the slew-rate current of your FC OTA may be too small. Would this apply to your case?

As pipeline ADCs are Nyquist-rate converters, you must check the SR performance of the S&H. You cannot expect having slowly varying input signals as in oversampled converters.

Paul