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Design >> Mixed-Signal Design >> 10b highspeed pipelined ADC
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Message started by ramakrishna on Oct 15^th, 2005, 9:38am

Title: 10b highspeed pipelined ADC
Post by ramakrishna on Oct 15^th, 2005, 9:38am

Hello all,

I am designing a 10b 150Msamples/sec with input bandwidth of 200Mhz. I was going through the IEEE publications and found the following paper
"10b 200Msps CMOS parallel pipeline ADC" L.sumanen, halonen.

There is a technique called "double sampling pipeline ADC" in which the ota is used in both clock phases to produce the residue.

I have designed earlier a 10b pipeline ADC arechitectures that could sample the input at 100Mhz, so if I use the same ota now in doubling sampling architecure the effective sampling rate will now be 200Msamples/sec.

I am not sure what could be the possible disadvantages with above approach to obtain 200Msamples/sec sampling frequency other than power dissipation compared to the Halonen's ADC refered above.

Please let me know what is the best architecure to use if I am looking for " 10b 150Msamples/sec with input bandwidth of 200Mhz".

Thanks,
Ramakrishna

Title: Re: 10b highspeed pipelined ADC
Post by sheldon on Oct 22^nd, 2005, 6:50am

Ramakrishna,

The right architecture depends on many factors. In
general, using a parallel architecture is an easy way
to increase the speed of an ADC. By operating ADCs
in parallel and offsetting the Sample and Hold times
you can increase the speed. Re-using the OTA would
allow you to double the speed at the same power.
There are probably constraints on the architecture of
the switched-capacitor stage in order to use double
sampling.

The design will also be limited by the usual constraints,
for example, aperature jitter. Twice as fast needs the
aperature glitter needs to be twice as small.

Using a parallel ADC introduces some new problems,
in particular, fixed-pattern noise. Unless the ADCs are
identical, there will be mismatch between the ADCs
resulting in "noise" in the output.

Best Regards,

Sheldon

Title: Re: 10b highspeed pipelined ADC
Post by ramakrishna on Nov 3^rd, 2005, 11:24pm

Hello Sheldon,
Thanks a lot for the reply.

Quote:

The design will also be limited by the usual constraints, for example, aperature jitter. Twice as fast needs the aperature glitter needs to be twice as small.

1.For the case with conventional pipelined ADC operating at 200Msps and double-sampling ADC operating at 200Msps, the aperture jitter requirement is the same. I could not understand this statement completely.

2. I have gone through some papers on non-idealities of double-sampling technique and parallel pipelined ADC, but none of them really give an estimate what is the limitation on the resolution and speed of the ADC because of those non-idealities. Is behavioral modeling only way to determine these limitations.

3. "10b 150Msps with analog bandwidth of 200Mhz with a Imax of 120mA" is it feasible to achieve using double sampling technique in pipeline ADC. Does anyone have better architecture suggestions.

After lot of literature study I could not come to a conclusion on this. Any suggestions/references will be of great help to me.

Thanks
Ramakrishna

Title: Re: 10b highspeed pipelined ADC
Post by rf-design on Nov 3^rd, 2005, 11:43pm

The simple view:

If matching determine the cap size of the first residue stage the OTA current is proportional to the cap size and clock. In the settling performance also the second order poles of the OTA come into playand these depend on technology and used VDSAT. So if you near the secondary poles of the OTA with your required settling time it makes sense to use a parallel architecture. If not it complicate your design. If you can calibrate the residue thresholds of the first stage you dramatic change the OTA-power/cap-size/clock-frequency relationship.

Title: Re: 10b highspeed pipelined ADC
Post by ramakrishna on Nov 4^th, 2005, 12:16am

Hi

Thanks for the quick response.

Quote:

If you can calibrate the residue thresholds of the first stage you dramatic change the OTA-power/cap-size/clock-frequency relationship.

i could not understand what you mean by calibrating the residue thresholds, does that mean calibrating the gain-error/settling error of the first residue stage.

Can you please explain me.

Thanks,
Ramakrishna

Thanks

Title: Re: 10b highspeed pipelined ADC
Post by rf-design on Nov 4^th, 2005, 5:45am

If the first residue stage is multibit you have a flash A/D. The threshold mismatches between the A/D and the D/A of the first residue only define that you need in the second residue a little bigger dynamic range than defined by the bit reduction.

The absolute mismatches of the D/A of the first residue stage could be corrected in the digital domain. Instead of composing the hole digital word of the complete pipeline converter of the individula residue results you add the residue results together. So if there is a mismatch the residue result to add has also some LSB contributions representing the true D/A level. If the first residue deliver 4bit you need 16 different residue results, or to compress the storage only the corrections.

The clue today is to extract the true D/A values from conversion statistics instead of using a calibration routine and stopping normal operation. That works in principle by assuming that the signal is uniform distributed within two ideal D/A levels. From the nonuniform distribution of individual level statistics you can recalculate the DNL of the first residue D/A.

The rest is analog standard work. Have fun!

Title: Re: 10b highspeed pipelined ADC
Post by ramakrishna on Nov 8^th, 2005, 4:07am

Hi,
I have not implemented calibration till now. do you have any references/material which would help me understand this technique in more detail.

Thanks,
Ramakrishna