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Design >> RF Design >> IIP3 and 1 dB Compression point
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Message started by ssk_288 on Oct 18^th, 2005, 2:07am

Title: IIP3 and 1 dB Compression point
Post by ssk_288 on Oct 18^th, 2005, 2:07am

Hi

Can anyone suggest me some paper which relates the IIP3 and 1 dB compression point to Drain current, gate overdrive etc.... for a LNA

Thanks

Regards
SUDHIR

Title: Re: IIP3 and 1 dB Compression point
Post by fab_jor on Feb 9^th, 2006, 10:46pm

Please, look at http://www.odyseus.nildram.co.uk/RFIC_Circuits_Page.htm and CMOS Differential L.N.A link !!!

Regards

Title: Re: IIP3 and 1 dB Compression point
Post by RFICDUDE on Feb 27^th, 2006, 6:42pm

The main reference for the CMOS IP3 is not correct in the refered website document.
Here is link to the author's presentation (Thomas Lee's Standford group)
http://www-smirc.stanford.edu/papers/cancun97s-chet.pdf
And here is the paper
http://www-smirc.stanford.edu/papers/cancun97p-chet.pdf

Also note that the web paper on LNA's is about differential LNAs, but the IP3 paper is on short channel single ended MOSFETs.

There was also a good characterization paper at RFIC 2005 on linearity of short channel MOSFETs.

Guofu Niu; Jun Pan; Xiaoyun Wei; Taylor, S.S.; Sheridan, D., "Intermodulation linearity characteristics of CMOS transistors in a 0.13 /spl mu/m process," Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE , vol., no.pp. 65- 68, 12-14 June 2005