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Measurements >> Phase Noise and Jitter Measurements >> Questions about simulation of PFD/CP and FD jitter
https://designers-guide.org/forum/YaBB.pl?num=1129700195

Message started by alexzxb on Oct 18^th, 2005, 10:36pm

Title: Questions about simulation of PFD/CP and FD jitter
Post by alexzxb on Oct 18^th, 2005, 10:36pm

Dear all,

According to Ken's paper of "phase noise and jitter", I need to get the jitter of PFD/CP and FD blocks to determine the overall jitter of the PLL.

Unlike oscillators, for PFD/CP and FD, input signals must be given to get pss and pnoise results. In the paper, it is said "a representive input" should be set for PFD/CP and FD. I wonder how to set the input.

For PFD/CP, a reference and feedback clock act as the input for PFD, should I add some delay between these two signals, how do I set the rise and fall time? For FD, the latter question is also bothering me.

Any answer and discussion is appreciated.