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Design >> High-Speed I/O Design >> ON LVDS TX
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Message started by navin_kumar on Oct 25th, 2005, 9:09pm

Title: ON LVDS TX
Post by navin_kumar on Oct 25th, 2005, 9:09pm

Hi all
i am going to design  lvds tx driver
i want to know how to model the package,pad and transmission line models for the simulation of the tx buffer
please any one give me good sugestions and links

Title: Re: ON LVDS TX
Post by ywguo on Oct 26th, 2005, 7:52pm

Hi, Navin,

You need get the package model from your package house to simulate accurately.

The transmission line model can be extracted using a lumped model. You can choose a lossless transmission line model, too.

Since the pad has parasitic capacitance which depends on its layout and ESD design, you'd better simulate with a real pad circuitry.  :)


Best regards,
Yawei

Title: Re: ON LVDS TX
Post by navin_kumar on Oct 28th, 2005, 3:32am

Hi ywugo ,
thabks for the reply
ya for the transient simulations we have to see all the model inclusion
can u please any good link for those model
thnks & regards
navin

Title: Re: ON LVDS TX
Post by ywguo on Nov 1st, 2005, 7:58pm

Hi, Navin,

Please refer to any SPICE or spectre manual for the transmissioni line model.


Best regards,
Yawei

Title: Re: ON LVDS TX
Post by SATurn on Oct 10th, 2006, 1:24pm

I would suggest also to model more accuratly the on-chip (long connections) or off-chip (PCB) transmission lines using ADS or "Polar" softwares. Specially in high-speed applications you must take into account the loss of line or reflections coming from each part.

Title: Re: ON LVDS TX
Post by justdoit on Sep 5th, 2007, 5:57am

Hi all ,
I do have a question on LVDS transmitter design . I am using a common mode feedback circuit to stabilize the output common mode voltage and I want to do the stability analysis for this feedback loop.For that I need to get the pole at the output of the LVDS driver .Can anyone suggest what all the resistances and capacitances that come into play while calculating this pole !!!!!

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