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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> ring vco https://designers-guide.org/forum/YaBB.pl?num=1130332597 Message started by vijay on Oct 26th, 2005, 6:16am |
Title: ring vco Post by vijay on Oct 26th, 2005, 6:16am Hi friends, could anyone guide me in getting a link to get the exact relation of frequency with current in a ring symmetric load ring vco.Using paper from maneatis, as one of guidance. Thanks in advance. |
Title: Re: ring vco Post by keble on Oct 30th, 2005, 12:45pm Hi Vijay, I posted a reply but it disappeared! Finger trouble I guess. Maneatis's 1996 paper gives F=sqrt(2*k*Id)/(n*Ceff) where: k= the beta (W/L*K') of one of the PMOS symmetric loads Id = half the buffer current n = number of stages in the ring Ceff = total capacitance that gets charged/discharged per stage Is this what you meant? It's quite straightforward to derive the equation Rob |
Title: Re: ring vco Post by vijay on Nov 2nd, 2005, 1:15am Thanks Rob, One more question.The two equally sized load transitors at a particular Vctrl, will carry same amount of current which when added will give half the buffer current. So to get the gain of ur VCO stage the first step would be to charactreize your load as then you can tell the frequency variation right.Is it a right approach. |
Title: Re: ring vco Post by semitao on Oct 15th, 2006, 8:14pm keble wrote on Oct 30th, 2005, 12:45pm:
Hi,Rob, Can you give some more detail formation about Maneatis's paper? Where can I find it? thanks. |
Title: Re: ring vco Post by LowJitter on Oct 18th, 2006, 5:01pm semitao wrote on Oct 15th, 2006, 8:14pm:
John G. Maneatis , "Low-Jitter Process-Independent DLL and PLL Based on self-Bias Techniques," IEEE Journal of Solid-State Circuits, vol.31, No.11 November, 1996 |
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