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Design >> Mixed-Signal Design >> Inverter delay
https://designers-guide.org/forum/YaBB.pl?num=1130609752

Message started by digital on Oct 29^th, 2005, 11:15am

Title: Inverter delay
Post by digital on Oct 29^th, 2005, 11:15am

Hi,

I have designed a simple inverter buffer chain with progressively upsized inverters to drive a large load. But when i put the values into hspice and caluculate the delay, the spice results are always smaller than my hand calculated values. Someone told me that its because of slope mismacth at input and output. Cud anyone plz comment on this issue?
Thanks

Title: Re: Inverter delay
Post by ywguo on Nov 1^st, 2005, 6:25pm

Would you please show more details, such as the calculated delay and the simulation results? Otherwise, you should not expect to get helpful comments. :)