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Design >> Analog Design >> output load consideration
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Message started by vijay on Nov 3^rd, 2005, 8:49pm

Title: output load consideration
Post by vijay on Nov 3^rd, 2005, 8:49pm

Hi friends,
I have a symmetric load differential VCO.How do I take care of the output load considerations in my design? Or how do i design my VCO with fanout considerations.

Thanks in advance.

Title: Re: output load consideration
Post by ywguo on Nov 7^th, 2005, 8:09pm

Hello,

It's just a capacitive load, which affects the oscillating frequency of the VCO. :)

Yawei

Title: Re: output load consideration
Post by vijay on Nov 9^th, 2005, 2:06am

Thanks,
But what I meant to say that, if I use this VCO in a PLL circuit, which in turn is acting as a clock.Then there has to be certain consideration for the load which the PLL has to drive.This is like fanout consideration in the digital design side.Since it will be the VCO which has to drive the load so how do I design a VCO taking this fanout or load consideration.

Title: Re: output load consideration
Post by ywguo on Nov 21^st, 2005, 9:12pm

Vijay,

Normally the PLL block must have digital interface. You'd better put some inverters at the output of the VCO. Then the unpredicted digital design don't load the VCO directly.

Best regards,
Yawei

Title: Re: output load consideration
Post by uncle_ezra on Nov 22^nd, 2005, 12:57am

Well normally u have a buffer in between so you can design them sort of independently.

Title: Re: output load consideration
Post by vijay on Nov 27^th, 2005, 8:18pm

Thanks,
This is the output buffer design,
I got it.
Thanks.
V

Title: Re: output load consideration
Post by singh on May 30^th, 2011, 5:22am

can ushare the buffer design?? i designed my VCO keeping 1pF at the load but if i increase load capacitance,the oscilation frequency increases.Please let me know the buffer design

Title: Re: output load consideration
Post by loose-electron on May 30^th, 2011, 6:09pm

singh wrote on May 30^th, 2011, 5:22am:

can ushare the buffer design?? i designed my VCO keeping 1pF at the load but if i increase load capacitance,the oscilation frequency increases.Please let me know the buffer design

um, probably decreases....