The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> bootstrapped clocks and sampling jitter
https://designers-guide.org/forum/YaBB.pl?num=1131185096

Message started by vivkr on Nov 5^th, 2005, 2:04am

Title: bootstrapped clocks and sampling jitter
Post by vivkr on Nov 5^th, 2005, 2:04am

Hi,

I would like to know if the use of a clock bootstrapping circuit offers potential for increased sampling jitter in a high-speed, high-resolution S&H.

Are there significant sources of sampling jitter in the on-chip circuitry used for the bootstrapping? I am looking at the architectures described by Abo et. al (JSSC, May '99), and Kaiser and Dessouky (JSSC, Mar. '01).

I don't see any information about the jitter introduced by on-chip clock generation and clock buffering circuitry, and I assume that for the normal cases (non-boosting, non-bootstrapping), the jitter from the signal generator is dominant. Is the same true for bootstrapped clocks? Are there any special design guidelines to be followed?

Regards
Vivek

Title: Re: bootstrapped clocks and sampling jitter
Post by ywguo on Nov 10^th, 2005, 8:13pm

Hello, Vivkr,

I think you are right. The dominant jitter source is the signal generator. And the non-overlapping clock generator may be a major jitter source, too. Normally the bootstrapped circuitry is small and a minor jitter source. :)

Best regards,
Yawei