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Design Languages >> Verilog-AMS >> Verilog-A RAM Model
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Message started by Zorro on Nov 21^st, 2005, 3:27am

Title: Verilog-A RAM Model
Post by Zorro on Nov 21^st, 2005, 3:27am

Hello everybody,

I've written a simple verilog-AMS model for a RAM. Now I have to rewrite that model, but in verilog-A.

I'am not very experienced in verilog-A and I'd like to know if it's possible to declare a matrix, as in Verilog-AMS eg. reg [7:0] memory [255:0].

The verilog-AMS code is:

`timescale 1s/1ns
`define width 8
`define length 256

module RAM_INOUT ( READ_NWRITE, ADDR, CE, DATA);

input READ_NWRITE, CE;
input [`length-1:0] ADDR;
inout [`width-1:0] DATA;

reg [`width-1:0] memory [`length-1:0]; // RAM 256x8: 256 8-bit words

assign DATA = (READ_NWRITE && CE) ? memory[ADDR] : 'hz;

always @(ADDR or READ_NWRITE or DATA or CE)

if (!READ_NWRITE && CE) memory[ADDR] = DATA;

endmodule

Or if you have any suggestion. Thank you.

Title: Re: Verilog-A RAM Model
Post by MokoKoya on Nov 23^rd, 2005, 7:29am

Hello Zorro,

I have had a little experience in Verilog-A, and in RAM models. When it comes to creating the memory matrix, I find it easy to do it in the following way.

If I have 256 lines of memory @ 8 bits each (for example), I multiply the two and declare memory as:

integer memory[256*8 -1:0];

In other words, make the matrix 1D instead of 2D. Now address 0 is assigned the first 8 bits of memory, address 2 the next 8 bits of memory and so on.

Hope this helps,
Andrew ;D

Title: Re: Verilog-A RAM Model
Post by Zorro on Nov 29^th, 2005, 1:07am

Hello Mokokoya,

Thanks for your idea of converting a 2D matrix into a 1D vector. This worked very well although was a little tricky when accesing and transfering addresses and data.

Thank you very much.

Title: Re: Verilog-A RAM Model
Post by Zorro on Dec 1^st, 2005, 4:50am

If someone is interested, here is the ram in verilogA using Mokokoya's idea of converting a matrix in a 1D vector.

`define DATA_BITS 8
`define ADDR_BITS 2

module ram_va(READ_NWRITE, ADDR, CE, DATA, REF, Qb);
input READ_NWRITE, CE;
input [`ADDR_BITS-1:0] ADDR;
input [`DATA_BITS-1:0] DATA;
output [`DATA_BITS-1:0] Qb;
inout REF;

electrical READ_NWRITE, CE;
electrical [`ADDR_BITS-1:0] ADDR;
electrical [`DATA_BITS-1:0] DATA;
electrical [`DATA_BITS-1:0] Qb;
electrical REF;

parameter integer MEM = (pow(2,`ADDR_BITS)*`DATA_BITS);
parameter real vth = 2.5;
parameter real dig_v = 5.0;

integer addr_aux;
integer ce_aux, r_nw_aux;
integer data_aux_in[`DATA_BITS-1:0]; //it's the value read from the input port DATA
integer data_aux_out[`DATA_BITS-1:0]; //it's the value assigned to the output port Qb
integer k, bit, i, m;
integer memory[MEM-1:0];

analog begin

ce_aux = 0;
r_nw_aux = 0;
addr_aux = 0;
bit = 0;

generate i(`DATA_BITS-1, 0) data_aux_in[i] = ((V(DATA[i]) > vth) ? 1: 0); // data_aux_in = DATA

generate i(`ADDR_BITS-1, 0) addr_aux = addr_aux +((V(ADDR[i]) > vth) ? 1 << i:0); // addr_aux = ADDR

r_nw_aux = (V(READ_NWRITE) > vth) ? 1:0; // r_nw_aux = READ_NWRITE

ce_aux = (V(CE) > vth) ? 1:0; // ce_aux = CE

for (k=addr_aux*`DATA_BITS;k<=(((addr_aux+1)*`DATA_BITS)-1);k=k+1) begin
if ((r_nw_aux==1)&&(ce_aux==1)) begin
data_aux_out[bit] = memory[k];
bit = bit+1;
end else if ((r_nw_aux==0)&&(ce_aux==1)) begin
memory[k]= data_aux_in[bit];
data_aux_out[bit] = 0.1n;
bit = bit+1;
end else begin
data_aux_out[bit] = 0.1n;
bit = bit+1;
end
end

generate i(`DATA_BITS-1, 0) V(Qb[i], REF) <+ data_aux_out[i] * dig_v;
end
endmodule