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Design >> RF Design >> LNA Matching
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Message started by joy on Nov 23^rd, 2005, 11:32pm

Title: LNA Matching
Post by joy on Nov 23^rd, 2005, 11:32pm

Hi,

I am facing a little problem in designing an input matching network for a 2.4G LNA. The problem is I am working in 65nm process and my bias current is limited to .75mA. So my cgs is very small, abt 50fF. Hence I have tried doing an inductive degeneration Ls to give gmLs/ Cgs = 50 ohms...however to tune out the large imaginary part, I need a very large inductor at gate...abt 50n..and that has a very poor Q of abt 2...So I fail to match.
I have tried another alternative, to put a parallel cap across Cgs to increase its value to arnd 300fF..that way I get matching, but because by adding extra cap, I am reducing fT, I am hurting my gain a lot and so its not that good.
If someone cud suggest a better/new way of dealing with thid, it will be very helpful.
Thanks and Regards,
Joy

Title: Re: LNA Matching
Post by milkdragon on Nov 28^th, 2005, 11:49am

Hi,

Sounds like to me that you are using a very small device. You can increase the device size, which can get you more Cgg and more Gm at the same time. I understand that there should be an optimum size for each process node. Try it and see if things work out.

Hope this help