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Design >> Mixed-Signal Design >> Adder design
https://designers-guide.org/forum/YaBB.pl?num=1132817923

Message started by Debo on Nov 23^rd, 2005, 11:38pm

Title: Adder design
Post by Debo on Nov 23^rd, 2005, 11:38pm

Hi,

I have to design an 8-bit adder in 0.25u technology and do the full layout. The constraint is to get minimum area-delay product..power is not a great constraint. But I have to get minimum prapagation delay * layout area.
Can someone suggest what could be a good topology for this case?
Thanks and Rgds, Debo