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Design >> Analog Design >> Symmetric delay cell
https://designers-guide.org/forum/YaBB.pl?num=1132831541

Message started by vijay on Nov 24^th, 2005, 3:25am

Title: Symmetric delay cell
Post by vijay on Nov 24^th, 2005, 3:25am

Hi,
I am trying to simulate a symmetric VCO, (Maneatis load).If I am supposed to start the design for a given frequency of operation, I would decide my number of stages and hence the delay of 1 stage. AS per the paper it is the use of variable resistance and not the Ceff that provides the variation in frequency. My question is how do I assume my Ceff at the first design entry for a 0.6um process.
Another doubt is whether the Ceff value will change with variation in my W values.
Thanks,
V

Title: Re: Symmetric delay cell
Post by vijay on Nov 28^th, 2005, 12:10am

Hi,
My another doubt is that if the single delay cell works fine, when the N number of stages are connected in feedback the oscillator fails to oscillate.
What could possibly be the reason.Calculation wise the sizing of the circuit is correct.
Help required,
Thanks in advance,
V