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Design >> Analog Design >> delay cell
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Message started by vijay on Nov 28^th, 2005, 6:09am

Title: delay cell
Post by vijay on Nov 28^th, 2005, 6:09am

Hi,
Require a help in simulating a single delay cell.
Case 1:
For Vctrl=2.25, I found out the required bias voltage for the tail transistor to maintain Vswing=Vdd to Vctrl at the output.It comes out to be 1.871V. The dealy cell shows the same Vswing even when a PWL source is used at its two inputs.
Case 2:-
When I attach a Cload = 71fF for a 0.6um process the swings in the two arms vary.The observed results are:-
When In+ = 5--2.25V; Vop- = 2.25--4.3V.
Simultaneously In- = 2.25--5V;Vop+ = 5--3V.
I cannot understand why this variation in the swing happens???
When the Cload is not connected the oputput swing behaves accurately:-Vop+ = 5--2.25V and Vop- = 5--2.25V.
What could be the possibel reason for this behaviour.

Further more should I use a Vpulse to calculate the time delay of this cell for this Vctrl.
Thanks in advance,
V