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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Jitter while testing ADC https://designers-guide.org/forum/YaBB.pl?num=1133235662 Message started by Sid on Nov 28th, 2005, 7:41pm |
Title: Jitter while testing ADC Post by Sid on Nov 28th, 2005, 7:41pm Hello, Does only "clock source" jitter affect my SNR while testing my ADC, or does the jitter in my "input signal" also matter? I am loaning a state-of-the-art low-jitter clock source for testing my 14 bit ADC, but I will still be using a "value price" function generator for my input signal. Do I have to worry about the jitter in my input signal? I will be using a band-pass filter to improve the harmonic distortion of the input signal before it is applied to my ADC. Thanks, Sid |
Title: Re: Jitter while testing ADC Post by ywguo on Nov 28th, 2005, 10:37pm Hi, Sid, I think the jitter in the input signal affects the testing because that jitter deteriorates the SNR of the input signal. However, the SNR of the input signal affects the testing directly. So just find the SFDR, SNR and THD parameters in the manual of your signal generator. To test such a high resolution ADC it is a good idea to filter the input signal if you have not good enough signal generator. :) Look into this problem from another perspective, the clock source and input signal are locked to the same reference timing clock. So we assume the clock source is phase locked to an sine wave w/o jitter (the input signal). So we only need know the jitter of the clock source. Best regards, Yawei |
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