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Design Languages >> Verilog-AMS >> AMS Beginer: Need help w/ AMS netlisting from HED
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Message started by Saroj Rout on Dec 4th, 2005, 2:49am

Title: AMS Beginer: Need help w/ AMS netlisting from HED
Post by Saroj Rout on Dec 4th, 2005, 2:49am

I am just starting to do mixed-mode top level simulation in AMS using Cadence environment.
I am interested in the following methodology:

1) Creat config view using Hierarchy editor. For every block I will selecting either a AMS model, transistor level model or verilog-A model.

2) Once I have created the config view, I want to netlist this particular config view into a AMS (or any other appropriate ) netlist.

3) I want to instatiate the above netlist in my testbench which is written in AMS language (NOT a schematic).

4) Use ncverilog (or any other appropriate simulator) to simulate the above AMS testbench.

5) Once simulated I want to use AWD viewer in cadence to view the result.

Here are my questions:

1) Once I create the config view, how do I create a AMS netlist of the whole hierarchy ?

2) If I am compiling my testbench in command line, how do I include the connect modules ?

3) If I use ncverilog to compile the AMS testbench, is it possible to use AWD to view the result ?

I am in severe time crucnch, any help will be greatly appreciated.

Thanks
Saroj Rout
Analog Designer

Title: Re: AMS Beginer: Need help w/ AMS netlisting from
Post by jbdavid on Aug 3rd, 2006, 6:03am

This is probably a year late, but maybe it will help someone..
( I was in severe time crunch then also, so not reading the forum)
a config view is a "configuration" of some "design" view..
you already have to have specified the design you want to configure..
In cadence this will generally be a schematic, so you also need symbols for all the blocks, devices you are putting in your design..
Alternatitvely you can just create a verilogams netlist of the top level..

you can specify psf format for your analog outputs, then AWD can read them, but wavescan can read both analog and digital signals

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