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Measurements >> Phase Noise and Jitter Measurements >> Phase Frequency detector gain
https://designers-guide.org/forum/YaBB.pl?num=1133817018

Message started by Tikka on Dec 5^th, 2005, 1:10pm

Title: Phase Frequency detector gain
Post by Tikka on Dec 5^th, 2005, 1:10pm

Hi,

This is related to a topic I put on the RF design section of this forum before I discovered this section.

http://www.designers-guide.org/Forum/?board=rfdesign;action=display;num=1133771609

I need to work out the gain for my model for the phase domain model of my Phase frequency detector. The actual circuit is of the flip flop type with one D-type triggered by the reference clock and another triggered by the divided VCO clock. The reset to both of them is the AND function of the two D-type output with a delay added for deadband compensation. When the UP output goes high the charge pump sources Icp and when Down goes high the charge pump sinks Icp. I think this is a fairly standard type of architecture. I believe my gain should be 2*Icp/2PI as there is a contribution during simulation for a frequency deviation and a similar contribution for a fixed phase offset and hence the reason for 2*Icp. Can anyone please confirm this to be true?

Thanks
Andy